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Design Languages >> Verilog-AMS >> Modelling phase delay
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Message started by Tom Johnson on Apr 21^st, 2004, 7:39am

Title: Modelling phase delay
Post by Tom Johnson on Apr 21^st, 2004, 7:39am

Hi,
Im involved in a synchronizer project and need to model the system. I have 1 clock signal running at XMHz and need to create a phase shifted version of it, where the phase shift varies sinusoidally between +- Ømax.
Basically i need to create a block of code that performs a variable phase shift Ø(t), as shown below and am wondering is this possible?
Thanks in advance
Tom
variable delay block
_________________
| |
Ø(t) = sin(t)
|________________|

Title: Re: Modelling phase delay
Post by Eugene on May 4^th, 2004, 7:47pm

I see two possibilities but I have never tried them.

(1) There is a "delay" element in VerilogA but I do not know if the delay can be a dynamic variable. If it can, you will have to add thetamax to the sinusoid so that you do not request a negative delay. (No non-causal elements allowed.)

(2) Perhaps you could create a PLL that tracks the XMHz clock. Then add a sinusoidal perturbation to the VCO input. If you get the scale the sinusoidal source correctly, I think the VCO should dither sinusoidally about the XMHz clock as desired.

Title: Re: Modelling phase delay
Post by Ken Kundert on May 4^th, 2004, 10:04pm

Another alternative is to simply create a new source that produces a signal with a sinusoidally varying phase rather than using a delay block with a sinuoidally varying delay.

Thus, if the first source uses
V(out1) <+ A*sin(2*`M_PI*fo*$abstime);
you can use
V(out2) <+ A*sin(2*`M_PI*fo*$abstime + `M_PI*sin(2*`M_PI*f1*$abstim));
to produce the second signal.

-Ken