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Design Languages >> VHDL-AMS >> Variable clock delay modelling
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Message started by Tom Johnson on Apr 21^st, 2004, 7:40am

Title: Variable clock delay modelling
Post by Tom Johnson on Apr 21^st, 2004, 7:40am

Hi,
Im involved in a synchronizer project and need to model the system. I have 1 clock signal running at XMHz and need to create a phase shifted version of it, where the phase shift varies sinusoidally between +- Ømax.
Basically i need to create a block of code that performs a variable phase shift Ø(t), as shown below and am wondering is this possible?
Thanks in advance
Tom
variable delay block
_________________
| |
Ø(t) = sin(t)
|________________|

Title: Re: Variable clock delay modelling
Post by George Suarez on Apr 29^th, 2004, 5:24pm

Hi,

Here is a code that I wrote for random numbers between A and minus A.

architecture random of random_num is

constant K : real := 1.3806503e-23;
signal Vth_op: real := 0.0;
signal rand: real := 0.0;
signal clk : bit :='0';

entity ... is...
end entity;

architecture ideal of .... is

signal rand1,rand2: real := 0.0;
signal clk : bit :='0';

begin
clk <= not clk after Tshrn;
process
variable unf : real;
variable seed1:integer := 2;
variable seed2:integer := 123123123;
begin
wait on clk;
Uniform(seed1,seed2,unf);
rand1 <= ROUND(unf*10.0);
--Multiply unf by 10 to obtain integer
end process;
break on rand1;
process
variable unf : real;
variable seed1:integer := 2;
variable seed2:integer := 123123123;
begin
wait on clk;
Uniform(seed1,seed2,unf);
rand2 <= unf;
end process;
break on rand2;

between_A_n_minusA == ((-1.0)**rand1)*rand2*A
end random;

This code may be freely distributed, I create it for a course project. Hope it helps.

gEoRgiE