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Measurements >> Phase Noise and Jitter Measurements >> Buffers, Dividers, ... Synch. Jitter computation
https://designers-guide.org/forum/YaBB.pl?num=1083599187

Message started by City on May 3^rd, 2004, 8:46am

Title: Buffers, Dividers, ... Synch. Jitter computation
Post by City on May 3^rd, 2004, 8:46am

Hello,

I'm investigating the phase noise floor due to buffers
and dividers in a very low-noise Tx system for CDMA.

From my experience in a past project and also confirmed
by The website's jitter paper, the timing jitter can be
approximated by evaluating the output voltage and
the slope at the so called "zero crossing". Measurements done on a designed PLL system proved
the validation of the zero crossing method for
the XTAL buffer noise.

The zero crossing approach implicitely assumes that the
next stage has very high gain which is not always the case at RF frequencies such as 4-8Ghz. I am wondering if the zero-crossing approximation is still valid because the transitions more smooth and the next stage will not be triggered at a single point such as in high gain systems. In 96 A. Hajimiri and T.H. Lee have introduced an interesting concept using ISFs. Wouldn't that be
a more general and precise method to evaluated the phase noise contribution of RF buffers ? Is there anybody who already did the link between both approachs ?

Cao-Thong