The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Mixed-Signal Design >> Settling time of Telescopic cascode opamp
https://designers-guide.org/forum/YaBB.pl?num=1083818774

Message started by ywguo on May 5^th, 2004, 9:46pm

Title: Settling time of Telescopic cascode opamp
Post by ywguo on May 5^th, 2004, 9:46pm

Hello,

When I simulate the settling behaviour of MDAC used in a stage for pipelined ADC, it shows very large overshoot (about 100mV) at SS corner, 3.0V, 125C.

The MDAC lies in a conventionally 1.5bit stage, made of a telescopic opamp and several capacitors and switches.

But at TT corner, 25C, 3.3V, and FF corner, -40C, 3.6V, the overshoot is very small (less than 10mV) and the telescopic opamp settles very fast.

The AC analysis shows that the phase margin is more than 75 degree. Especially when the capacitance loading is large, the phase margin approaches 80 degree. I though that is normal for a two-pole system when its settling behaviour is the most concern.

Could you help me? Tell me how to improve the settlng behaviour.

Best regards,

Yawei Guo

Title: Re: Settling time of Telescopic cascode opamp
Post by Faisal Mateen on May 12^th, 2004, 10:18am

Hello,

One reason for this behavior could be due to the variation in the currents in the main opamp (at different corners) if you are using a master bias current source. Also the "gm" of the transistor varies at different corners. One reason could also be the switch (variation of resistance at different corners) used to connect the feedback capacitor with the opamp input (during the hold phase/multiplication phase)

Also if you are using ac analysis it will be hard to correlate the phase margin of the opamp with the settling time analysis for the switched capacitor gain stage, because of the dynamic nature of the capacitive load.

Title: Re: Settling time of Telescopic cascode opamp
Post by microant2000 on Nov 10^th, 2004, 5:54am

hi,Yawei
i want to ask you a question,how do you measure the phase margin of op-amp,in open-loop or close-loop condition? as you know,in SC circuits the signal is discrete,and i don't know how to carry out AC analysis,
thanks a lot
microant