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Design Languages >> VHDL-AMS >> Interpolation Computing Code.What's wrong in it?
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Message started by cyjim on Jun 3^rd, 2004, 11:14pm

Title: Interpolation Computing Code.What's wrong in it?
Post by cyjim on Jun 3^rd, 2004, 11:14pm

I wrote the code below,but I can't compile it successfully.Can you help me,what's wrong in it?
Thanks a lot!

cyjim

-------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity lineinter is
port(reset:in std_logic;
clk:in std_logic;
xe,ye:in signed(15 downto 0);
cpx1,cpx2,cpy1,cpy2:0ut std_logic);
end entity lineinter;

architecture lineinter_arch of lineinter is
begin
process(clk,reset,xe,ye)
variable c,d,e,f:std_logic;
variable q:signed(31 downto 0);
variable r,s:signed(15 downto 0);
begin
if reset='0' then q:=(others=>'0');r:=(others=>'0');s:=(others=>'0');
elsif clk'event and clk='1' then
a:loop
q:=xe*s-r*ye;
if (xe(15)='0') and (ye(15)='0') then
if q(31)='0' then c:='1';q:=q-ye;r:=r+1;
else e:='1';q:=q+xe;s:=s+1;
end if;
end if;
if (xe(15)='1') and (ye(15)='0') then
if q(31)='0' then e:='1';q:=q+xe;s:=s+1;
else d:='1';q:=q+ye;r:=r-1;
end if;
end if;
if (xe(15)='1') and (ye(15)='1') then
if q(31)='0' then d:='1';q:=q+ye;r:=r-1;
else f:='1';q:=q-xe;s:=s-1;
end if;
end if;
if (xe(15)='0') and (ye(15)='1') then
if q(31)='0' then f:='1';q:=q-xe;s:=s-1;
else c:='1';q:=q-ye;r:=r+1;
end if;
end if;
cpx1<=c;cpx2<=d;cpy1<=e;cpy2<=f;
exit a when r=xe and s=ye;
end loop a;
end if;
end process;
end architecture lineinter_arch;

Title: Re: Interpolation Computing Code.What's wrong in i
Post by Andrew Beckett on Jun 4^th, 2004, 1:02am

I tried compiling this with:

Code:

ncvhdl -ams code.vhd

and it gave some fairly clear errors:

Code:

ncvhdl -ams code.vhd
ncvhdl: 05.10-s012: (c) Copyright 1995-2004 Cadence Design Systems, Inc.
cpx1,cpx2,cpy1,cpy2:0ut std_logic);
|
ncvhdl_p: *W,REQSEX (code.vhd,9|21): no separator between number and identifier [13.2].
cpx1,cpx2,cpy1,cpy2:0ut std_logic);
|
ncvhdl_p: *E,EXPUSN (code.vhd,9|20): expecting an expanded name [6.3].

If you look at the line in your code it is complaining about:

Code:

cpx1,cpx2,cpy1,cpy2:0ut std_logic);

you'll see you've written 0ut instead of out. If I fix that, it compiles OK.

You didn't say which tool you were using here, but the lesson is probably to pay attention to the error messages!

Regards,

Andrew.

Title: Re: Interpolation Computing Code.What's wrong in i
Post by cyjim on Aug 22^nd, 2004, 5:40pm

Hi,Andrew!
Thanks a lot for your reply to my topic. I have put the problems straight.

best regards,
cyjim