The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> RF Design >> CMOS Mixer Chopping & Multiplication and Noise
https://designers-guide.org/forum/YaBB.pl?num=1087297465

Message started by wccheng on Jun 15^th, 2004, 4:04am

Title: CMOS Mixer Chopping & Multiplication and Noise
Post by wccheng on Jun 15^th, 2004, 4:04am

Dear all,

For the Noise Figure Problem:
In the previous reply in this newsgroup, someone said that the Chopping mixer is lower NF compared with the Multiplication one. However, in the chopping principle, the large signal switching will create larger noise compared with the multiplication. Morevoer, the feed-through effect to the IF. It will make the noise much larger than the multiplication mode.

In the simulation, the chopping is smaller NF than the multiplication. WHY? As I think, the IF power in the chopping mixing is larger than the multiplication mixing. Therefore, SNRout is larger and make the NF lower. Do my this explanation correct?

For the Chopping and Multiplication Problem:
In the chopping, the transistor will switch between cut-off and saturation region. However, as the transistor switch to the saturation region, the impedance will be larger compared with the linear. Then, the output power will lower in the IF. Actually, is the chopping switching between cut-off and LINEAR instead of the cut-off and SATURATION?

On the other hand, could CMOS working as multiplier? I means working as the two sin waves in multiplication. Is it just could work at sub-threshold region only?

I am really your expert helping. :-/

Best Regards,

wccheng