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Design Languages >> Verilog-AMS >> array of random numbers
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Message started by Jeremy Lubkin on Jul 2^nd, 2004, 2:51pm

Title: array of random numbers
Post by Jeremy Lubkin on Jul 2^nd, 2004, 2:51pm

I am trying to generate an array of uniformly distributed numbers at the beginning of a verilogA module. I want this array to be initialized at startup.

The ultimate goal is to generate a noise signal - this signal would consist of equal spaced, equal magnitude, random phase sine waves that are added to the input. The way I am doing this is going thru a for loop (i = num noise sources) and adding in a sine wave to a running noise signal - which I add to the input signal at the end.

I discovered I cannot have a random function in a loop - so I was going to pre-generate an array (longer than any expected number of sources) of random variables and just access this array within my loop.

I dont know how to set up this array of unif. random numbers.

Would appreciate input.
Thanks,
Jeremy

Title: Re: array of random numbers
Post by Andrew Beckett on Jul 6^th, 2004, 8:46pm

This is due to be fixed in this PCR:

PCR: 585550
Title: random, dist_normal etc cannot be used in iterations

It was supposed to be in IC5033USR2 and IC5141, but for some reason isn't, which I'm looking into right now.

Andrew.