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Design >> Mixed-Signal Design >> What is 5V tolerant?
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Message started by ywguo on Jul 5^th, 2004, 10:29pm

Title: What is 5V tolerant?
Post by ywguo on Jul 5^th, 2004, 10:29pm

Hello,

What is the definition of 5V tolerant? Is there any paper, standard, or textbook that define and discuss the structure of 5V tolerant I/O?

Thanks

Yawei Guo

Title: Re: What is 5V tolerant?
Post by Nader on Jul 30^th, 2004, 2:52pm

A few years ago when I worked on some I/O blocks for us 5V tolerant meant that our internal operating voltage within the chip was 3.3V but our I/O's had to be able to receive 5V signals from outside. In other words we were suppose to be able to interface with the 5V world out there while operating at 3.3V internally.

I am not sure if this is a universal definition or not. There were a few ways to deal with this. The one I liked best and didn't use it myself was published once in EEDesign I think by two Korean guys. Their interface was able to automatically adjust to the outside signal level with a remarkably simple circuit made of a few diodes and resistors. I wish I had kept that circuit. But I didn't.

You should search the literature with keywords like "level shifters" and that sort of thing and you will find something to work with.

Regards,

Nader