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Simulators >> Circuit Simulators >> How to design a PLL according to specs?
https://designers-guide.org/forum/YaBB.pl?num=1089161992

Message started by hanjiemy on Jul 6^th, 2004, 5:59pm

Title: How to design a PLL according to specs?
Post by hanjiemy on Jul 6^th, 2004, 5:59pm

hi, every one.
for low vco jitter, I use hspice vco macro instead LC tank vco.

*********************************************
vcc vcc 0 2.7
vee vee 0 0

xin2 Vtune 0 out1 out1b vco f0=141meg kf=35meg phi=0.0 out_off=0.0 out_amp=0.1

.macro vco in inb out outb f0=100k kf=50k phi=0.0 out_off=0.0 out_amp=1.0
gs 0 s poly(2) c 0 in inb 0 '6.2832e-9*f0' 0 0 '6.2832e-9*kf'
gc c 0 poly(2) s 0 in inb 0 '6.2832e-9*f0' 0 0 '6.2832e-9*kf'
cs s 0 1n
cc c 0 1n
e1 s_clip 0 pwl(1) s 0 -0.1,-0.1 0.1,0.1
e out r s_clip 0 out_off '10*out_amp'
eb outb r s_clip 0 out_off '-10*out_amp'
.ic v(s)='sin(phi)' v(c)='cos(phi)'
vr r 0 1.86
.eom

*****************************************************

but after a few micro secs, it lost oscillation. ( this macro cell is no problem). can u encounted problem like this. what happen????

thanks