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Design Languages >> Verilog-AMS >> Simulating and integrating netlists with AMS
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Message started by aznaragorn on Jul 7^th, 2004, 12:46pm

Title: Simulating and integrating netlists with AMS
Post by aznaragorn on Jul 7^th, 2004, 12:46pm

I am trying to simulate 4 blocks, let's say 2 behaviorly written in verilog ams language, and 2 defined schematically in Virtuoso. I am basically trying to do both system level simulation and transistor level simulations at the same time. What is the best way to approach this?

Right now I am attempting to generate verilog code for all four blocks by using an AMS netlister and using +modelpath to use analog primitives defined in spectre. Thus, I am generating AMS code for all four blocks.

Title: Re: Simulating and integrating netlists with AMS
Post by Andrew Beckett on Jul 7^th, 2004, 9:26pm

You don't give a whole lot of details, but yes, that would be the right thing to do.

What do you have on top? Schematic or netlist? It doesn't necessarily matter though...

What you can do is to compile the verilog code into your library:

ncvlog -ams -work yourLibName -use5x code.vams

Then in DFII create a config view (File->New->CellView,
choose "Hierarchy Editor" as the tool), and configure the
top cellView (be it verilog-ams code or a schematic), and then use the Plugins->AMS in the hierarchy editor to set up the simulation and run from there.

Or you can use the standalone "amsdirect" command to create the netlists, and then compile yourself. Easier still, you can use the standalone "amsdesigner" command to do all the netlisting, compilation, and run the simulation.

Regards,

Andrew.