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Simulators >> Circuit Simulators >> Simulation using Cadence virtuoso layout
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Message started by Vignesh on Jul 9^th, 2004, 3:13pm

Title: Simulation using Cadence virtuoso layout
Post by Vignesh on Jul 9^th, 2004, 3:13pm

Hi,

Anyone knows how to simulate the layout after finishing DRC, extraction and LVS. I use analog environment and also give stimuli like Vdd=2.5V and gnd=0V. But when I simulate the layout I still get 0V output. btw I am doing a transient simulation. Can anyone help me with this ?

Thanks
-vignesh