The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Simulators >> Circuit Simulators >> Post layout simulation problem
https://designers-guide.org/forum/YaBB.pl?num=1089597374

Message started by Vignesh on Jul 11^th, 2004, 6:56pm

Title: Post layout simulation problem
Post by Vignesh on Jul 11^th, 2004, 6:56pm

Hi,

I have problems with post layout simulation in Cadence. When I simulate the analog_extracted view, I get a spectre error saying -

"Error found by spectre during hierarchy flattening.
_v0:Terminals must not be connected together (to node '0')."

If someone could help me with this it would be nice.
Thank you,
Vignesh

Title: Re: Post layout simulation problem
Post by Andrew Beckett on Jul 13^th, 2004, 2:16am

What it means is that you have a voltage source with the terminals connected together (i.e. what the message says).

Something like this:

v1 (0 0) vsource dc=2

Andrew.