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Design Languages >> Verilog-AMS >> Segmentation of signal
https://designers-guide.org/forum/YaBB.pl?num=1089662274

Message started by aznaragorn on Jul 12^th, 2004, 12:57pm

Title: Segmentation of signal
Post by aznaragorn on Jul 12^th, 2004, 12:57pm

I am trying to use connect modules to use both analog and digital inverters. right now my code looks like this:

module test();

reg a;
logic a;
wire b,c,d;
logic b,c,d;
wire temp;
logic temp;
initial a = 0;
initial begin
forever a = #100 ~a;
end
assign temp = a;
analog_inv a1 (temp,b);
analog_inv a2(b,c);
endmodule

I have 2 connect modules defined elsewhere called a2d and d2a which are similiar to the ones posted on the designers guide website.

I get this error message on the line analog_inv a2(b,c):
ncelab : Segmentation of a signal between analog ports is illegal

Any ideas on what this means and how to fix it?

Title: Re: Segmentation of signal
Post by Andrew Beckett on Jul 13^th, 2004, 2:45am

What version are you using? I think this was fixed in LDV51...

Andrew.

Title: Re: Segmentation of signal
Post by aznaragorn on Jul 14^th, 2004, 12:34pm

I am using ncverilog 04.10. So how do i get past this problem?

Thanks in advance.

Title: Re: Segmentation of signal
Post by Andrew Beckett on Jul 14^th, 2004, 1:39pm

Using a later version would be the simplest solution.

The problem is quite complex, and I don't have time to research precisely what is causing it and if there is a workaround. Using LDV51 or IUS53 would be the quickest solution.

Andrew.

Title: Re: Segmentation of signal
Post by aznaragorn on Jul 22^nd, 2004, 12:11pm

LDV update got past this error, thanks.