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Design >> RF Design >> Fractional -N PLL
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Message started by pan137 on Jul 16^th, 2004, 2:29am

Title: Fractional -N PLL
Post by pan137 on Jul 16^th, 2004, 2:29am

Hello,
Can I get any document which has a very good explanation on Fractional - N PLL? In Fractional-N PLL they say that the feedback divider factor continuously keeps on changing. If this is the case then how is the lock generated as it is impossible to have both the input clock and feedback clock perfectly phase locked with changing feedback division factor?

thanks

Title: Re: Fractional -N PLL
Post by Dave on Aug 4^th, 2004, 6:47am

You're right, a fractional N pll is never really locked in the sense that the output of the PFD goes to zero. It is locked in the sense that the output of the VCO is a multiple of the comparison frequency, with that multiple being a non-integer. It isn't locked in the sense that the 2 inputs to the PFD converge on 2 signal's that are phase locked. Desiging a lock detector for a fractional N loop is an interesting task, one that I'm still thinking of.