The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> Connecting Registers to Analog Ports
https://designers-guide.org/forum/YaBB.pl?num=1090523650

Message started by aznaragorn on Jul 22^nd, 2004, 12:14pm

Title: Connecting Registers to Analog Ports
Post by aznaragorn on Jul 22^nd, 2004, 12:14pm

I always get the error: "analog ports can't be driven by registers directly" from ncelab when I connect registers to ports of electrical discipline ( I have connectmodules to deal with this). If I have wires connect these registers to the ports I don't get these warning messages. Is there anything fundamentally wrong with connecting registers to analog ports?

Title: Re: Connecting Registers to Analog Ports
Post by Andrew Beckett on Jul 27^th, 2004, 3:02pm

Have you moved to a more recent version of the tools (LDV51
or IUS53) as I suggested before in a previous similar posting? If not, does this still happen with the newer versions?

Regards,

Andrew.

Title: Re: Connecting Registers to Analog Ports
Post by aznaragorn on Jul 27^th, 2004, 4:33pm

Yes I have moved to the new LDV and the errors still persist.

Title: Re: Connecting Registers to Analog Ports
Post by Andrew Beckett on Jul 27^th, 2004, 9:51pm

In that case, can you post a small example which illustrates this? Also, can you post what "ncsim -version" returns?

Thanks,

Andrew.

Title: Re: Connecting Registers to Analog Ports
Post by aznaragorn on Jul 28^th, 2004, 5:58pm

ncsim -version returns:
TOOL: ncsim 05.10-s011

Code to generate error:

module test();

reg a;
logic b;

initial a=0;
initial forever a = #100 ~a;

analog_inv a1(a,b);
endmodule

module analog_inv(a,b);
input a;output b;
electrical a,b;
real outval;

analog begin
@(above(V(a) - 1.65)) outval = 0.0;
@(above(1.65 - V(a)) outval = 3.3;
V(b) <+ transition(outval,0,1n);
end
endmodule

I am using the sample connect module library cadence provides in the install directory.
I get an error something like :
Registers can not drive analog ports directly.

Title: Re: Connecting Registers to Analog Ports
Post by Andrew Beckett on Jul 30^th, 2004, 12:38am

There is an outstanding PCR for this problem - PCR 694264.

The problem is that a register cannot connect to an analog port if the register is at the top-level (driving analog), since this is not supported by ncelab.

Supporting this case from the digital elaborator involves non-trivial
amount of work, which is why it hasn't been implemented yet.

There's a simple workaround - use an assign statement, and then connect the assigned net to the analog block:

Code:

`include "disciplines.vams"

module test();

reg a;
logic b,c;

initial a=0;
initial forever a = #100 ~a;

assign c=a;

analog_inv a1(c,b);
endmodule

module analog_inv(a,b);
input a;output b;
electrical a,b;
real outval;

analog begin
@(above(V(a) - 1.65)) outval = 0.0;
@(above(1.65 - V(a))) outval = 3.3;
V(b) <+ transition(outval,0,1n);
end
endmodule

(note, I corrected the missing parenthesis in your code too).

Regards,

Andrew.

Title: Re: Connecting Registers to Analog Ports
Post by aznaragorn on Jul 30^th, 2004, 11:03am

Thanks, I figured out the temporary solution using nets, I was just wondering if there was something i was doing wrong. I have another question on this LDV update to 5.1. Some of our code no longer works in the new LDV, we get an error like this at the elaboration stage :
ncelab: *internal* (cu_propagate_expand -width conflict)

The problem occurs when we try to connect the output of a module to the top level through a vector net that is bit selected instead of using a scalar net.

For example:

module inside_module( insideout)
output insideout;
reg insideoout;
endmodule

module top()
output [1:0] topout;
wire [1:0] topout;

inside_module( .insideout(topout[1]))
endmodule

A funny thing about the error is that it only occurs when we have wreals. The engineer who has written the modules contacted Cadence but all they have told him so far is that it is a bug. Anyone experienced something similiar (cu_propagate_width errors) or have a suggestion?

Title: Re: Connecting Registers to Analog Ports
Post by Andrew Beckett on Aug 2^nd, 2004, 1:25am

I did some searching. This seems to have been the only reported instance of this problem, and so I suspect it is a bug in the specific situation you have, as you have been told.

Note, your example below is full of syntax errors (missing semicolons, missing instance name), and does not show the problem (it doesn't have any wreals in it, which you mention as being related).

Regards,

Andrew.

Title: Re: Connecting Registers to Analog Ports
Post by jbdavid on Nov 1^st, 2004, 7:38pm

wreals are not currently supported in a bus in the cadence implementation. This is a known issue, and is documented in the kp&s.

the register issue is the same one that prevents you from declaring a register as an output at the top level
( remember having to add a whole bunch of assign statements to a verilog-XL model for the same reason. )
If you do it at a lower level of the design, a net is added when you connect the module into the testbench.. and this "hides" that requirement..
basically you need a net there that you can insert the connect module on.. a register isn't quite the same kind of thing in verilog.. so there is a fundamental issue here..
I think there is also a problem (at least in ncelab) if you have an assign statement that contains some logic..
between two electrical nets..
wire a, b;
assign b = !a;

(where a is an electrical output of a lower module and b is an electrical input of a lower module.. )

jbd