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Design >> High-Speed I/O Design >> deterministic jitter in serdes receive data
https://designers-guide.org/forum/YaBB.pl?num=1090909093

Message started by feiyue on Jul 26^th, 2004, 11:18pm

Title: deterministic jitter in serdes receive data
Post by feiyue on Jul 26^th, 2004, 11:18pm

Dear all,

who knows the jitter concept well about Serdes and the deterministic jitter's PSD? Is it uniform distribution or other kind of distribution? I am doing some system simulation and not clear how to deal with this kind of jitter? I will greatly appreciate for your help!

feiyue

Title: Re: deterministic jitter in serdes receive data
Post by DReynolds on Mar 30^th, 2005, 6:34am

feiyue, deterministic jitter can have many different kinds of psd depending on the cause. Being deterministic, it could be relaled to the data pattern itself or it could from an interfering tone like an clock.

Can you explain a little more about the purpose of the sims you are doing... it might make it easier to understand what to suggest.

David Reynolds

Title: Re: deterministic jitter in serdes receive data
Post by Paul on Mar 30^th, 2005, 10:39pm

Feiyue,

the way most shorts-distance standards (ethernet, fibre channel, InfiniBand, etc) apply jitter to the input is signal is explained in this document:
ftp://ftp.t11.org/t11/pub/fc/mjsq/04-101v4.pdf

Modeling it is uniform is OK as a first estimate, but probably you want to develop a more accurate model based on this spec later.

Paul

Title: Re: deterministic jitter in serdes receive data
Post by feiyue on Mar 31^st, 2005, 8:19pm

hi David and Paul,

I was assigned to design a 1.25Gbps serdes receiver and need to modeling the receivered data with jitter for circuit simulation.

Just as Paul have said,I model it as uniform distribution,
I think it is enough for circuit simulation.

Thanks both of you!

feiyue