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Design >> RF Design >> Postlayout in tsmc 0.18um PDK
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Message started by CDR on Aug 3^rd, 2004, 5:26pm

Title: Postlayout in tsmc 0.18um PDK
Post by CDR on Aug 3^rd, 2004, 5:26pm

Anybody works on RF IC design using tsmc 0.18um PDK?

I am now using tsmc 0.18um CMOS PDK under cadence envioronment.

When I do the postlayout simulation of my double edge DFF at 5GHz
clock,10Gbps input data,possibly because the extracted parasitic caps is
very small,all around 10fF,below 20fF.There is warning of "
I155._inst96: Vgd has exceeded the oxide breakdown voltage of Vbox=4.08
V"
I155._inst99: Vgs has exceeded the oxide breakdown voltage of Vbox=4.08
V"
The simulation is very slow and finally can't converge, I guess the
simulation result will be wrong. But the schematic simulation is correct
and converge.

Anybody could give me some hints?

Thanks a lot.