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Design Languages >> Verilog-AMS >> Electrical to wreal interface
https://designers-guide.org/forum/YaBB.pl?num=1092075806

Message started by aznaragorn on Aug 9^th, 2004, 11:23am

Title: Electrical to wreal interface
Post by aznaragorn on Aug 9^th, 2004, 11:23am

I'm having some trouble trying to convert an electrical node to a wreal. I have a module within my top level module, whose output (voltage) i want to assign to a wreal at my top level. So something like:

module inside_module (out)
output out;
electrical out;
//behavioral code
endmodule

module top_module ( out);
output out;
wreal out;
electrical inside_out;
inside_module mod1 ( inside_out);

//I want to do something like:
assign out = V(inside_out);

endmodule

I keep on running into analog and digital interface issues when i try different solutions; the assign statement doesn't work because you can't sense transitions on analog access functions. I tried using a real to store the value in an analog block like this:
analog begin
inside_out_temp = V(inside_out);
end
and then doing this:
assign out = inside_out_temp;

Unfortunately since inside _out_temp is defined in the analog block, it is also considering analog owned and cannot be assigned to a digital signal (the wreal out).
I must be missing something really simple here. Any ideas? Thanks in advance, this forum has been very helpful.

Also, is there any way of using connect modules, or something similiar for wreal to electrical and vice versa interfaces.

Title: Re: Electrical to wreal interface
Post by jbdavid on Nov 1^st, 2004, 6:48pm

What you have to do is

wreal out;
real out_temp;

assign out = out_temp;
analog begin
out_temp = V(inside_out);
end

but you don't HAVE to have the analog block to access
the voltage, and you probably dont want
a digital event on every timestep,
So you might want to gate this with a sampleing clock
that could be a logic event

module top_module (input sclk, output out);
logic sclk;
wreal out;
electrical inside_out;
real out_temp;
inside_module mod1 ( inside_out);

//I want to do something like:
assign out = out_temp;

always @(posedge sclk) out_temp = V(inside_out);

endmodule

// of course if you don't want an external event controlling the sample time, you can experiment
with simple fixed time periods or a threshold
based update

always @(cross(out_temp-V(inside_out)-vth)
or cross(V(inside_out)-out_temp-vth))
out_temp = V(inside_out);

I haven't tried that, because I've always found there is a good clock to use for the sampling function I need to use.