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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> Order of execution at a timestep in Verilog https://designers-guide.org/forum/YaBB.pl?num=1092599412 Message started by sutapanaki on Aug 15th, 2004, 12:50pm |
Title: Order of execution at a timestep in Verilog Post by sutapanaki on Aug 15th, 2004, 12:50pm Hi, I need some help with the following Verilog code. If someone understands this, please respond. My question is about the order of execution during one time step. In the code I have it goes like this: 1: always 2: begin 3: #50 clk <= 1'b0; 4: #50 clk <= 1'b1; $display($time, "clk%b", clk) ; //here clk will be clk == 1'b0 because of the non blocking assignment 5: end 6: always @(posedge clk) 7: begin $display($time, "clk%b", clk) /*I expected different behavior here: I expect clk == 1'b0. As it is above. That is what I expect from a non blocking assignment when the timestep (100) has not finished yet. The simulation shows clk == 1'b1. So the non blocking assignment is executed not at the end of the time step but somewhere in the midle - before the event it trigers. This surprises me*/ 8: if(clk === 1'b1) 9: clk1 <= clk; 10: end |
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