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Design Languages >> VHDL-AMS >> How to design a Latch?
https://designers-guide.org/forum/YaBB.pl?num=1093223399

Message started by cyjim on Aug 22^nd, 2004, 6:09pm

Title: How to design a Latch?
Post by cyjim on Aug 22^nd, 2004, 6:09pm

Hi,all!
I've been in trouble with my design for days,I have to ask for ur help now.

I'd like to design a Latch,which works as below:

D(7 downto 0) is the input of the Latch,while A(7 downto 0) ,B(7 downto 0) ,E(7 downto 0) and F(7 downto 0) are the four outputs of the Latch.Ctr(1 downto 0) is the control variable. When Ctr="00","01","10"and "11", input D was sent to output A,B,E and F respectively.

My design tool is Quartus II,I hope you can give me some advices or opinions.

I'm eager to hear from you,Thanks a lot!

Title: Re: How to design a Latch?
Post by pktan on Jan 19^th, 2005, 12:52am

Try This.

library ieee;
use ieee.std_logic_1164.all;

entity test is port(
D : IN std_logic_vector(7 downto 0);
Ctr : IN std_logic_vector(1 downto 0);
A : OUT std_logic_vector(7 downto 0);
B : OUT std_logic_vector(7 downto 0);
E : OUT std_logic_vector(7 downto 0);
F : OUT std_logic_vector(7 downto 0)
);

end;

architecture behave of test is
begin

PROCESS(Ctr)
BEGIN

if(Ctr = "00") then
A <= D;
elsif(Ctr="01") then
B<= D;
elsif(Ctr="10") then
E<= D;
elsif(Ctr="11") then
F<= D;
end if;

END PROCESS;

end behave;

Title: Re: How to design a Latch?
Post by Nisha on Jan 27^th, 2005, 9:24pm

Hi!
the code above will not synthesise a latch.. this is just a basic demux.. or decoder.
If you need a latch, you have to put this inside a process and trigger it with a clock'event and edge.

library ieee;
use ieee.std_logic_1164.all;

entity test is port(
Clk:in std_logic;
D : IN std_logic_vector(7 downto 0);

Ctr : IN std_logic_vector(1 downto 0);
A : OUT std_logic_vector(7 downto 0);
B : OUT std_logic_vector(7 downto 0);
E : OUT std_logic_vector(7 downto 0);
F : OUT std_logic_vector(7 downto 0)
);

end;

architecture behave of test is
begin

PROCESS(Clk)
BEGIN
if clk'event and clk= '1' then -- positive edge triggered
if(Ctr = "00") then
A <= D;
elsif(Ctr="01") then
B<= D;
elsif(Ctr="10") then
E<= D;
elsif(Ctr="11") then
F<= D;
end if;
end if;
END PROCESS;

end behave;

The absence of the elsif condition in the clk leads to a latch.
Also remember that if leads to implied priority...in case that is not desired use a 'case' statement.

Title: Re: How to design a Latch?
Post by Paul on Jan 28^th, 2005, 3:06am

Hello,

I am certainly not an expert in this domain, but it seemed to me the edge sensitivity would be synthesized as a kind of FF. If you want to get a latch, shouldn't the process be CTR and CLK sensitive, but only sensitive to the level of clock and not the edge? I.e. If clk='1' and the process is triggered by CTR, the value would still be updated. Maybe Nisha can comment on that.

Paul