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Design >> Analog Design >> Sample and hold circuit
https://designers-guide.org/forum/YaBB.pl?num=1093229921

Message started by vivekrc on Aug 22^nd, 2004, 7:58pm

Title: Sample and hold circuit
Post by vivekrc on Aug 22^nd, 2004, 7:58pm

I designed a sample and hold circuit by using a capacitance, a analog switch and a voltage follower. This design works fine for an input frequency of 5 MHz and a clock frequency of 100 MHz.
What should i do in order to run the same design for an input frequency of 125MHz and a sampling frequency of 2.5GHz.
I have designed an analog switch using six transistors(3 PMOS and 3 NMOS)