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Design Languages >> VHDL-AMS >> signed logical operations in VHDL
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Message started by neocool on Sep 10^th, 2004, 11:06am

Title: signed logical operations in VHDL
Post by neocool on Sep 10^th, 2004, 11:06am

Hi,
I am fairly new to VHDL.
I am designing BPSK modulator and want it to output unsigned or 2's compliment format depending on the register settings I choose (so software selectable). I am wondering, how would you work with unsigned and 2's compliment in VHDL. Do you have to do all math manually or there are any special functions that can sum/subtract two 2's compliment numbers automatically? I have to use multiplication and addition of signals in my code.

Thanks for any help in advance

Title: Re: signed logical operations in VHDL
Post by Paul on Sep 13^th, 2004, 12:57pm

Hello,

you can define your signals as unsigned, a predefined signal type. All operations on this type are predefined too.
As far as I remember, synthesis tools also understand 'unsigned' correctly and the signals will be synthesized as a n-bit logic signal.

Paul

Title: Re: signed logical operations in VHDL
Post by neocool on Sep 21^st, 2004, 11:04am

thanks
I've partially answered this question myself. Apparently, signed ports did not work for me. I had to cast slv to signed, then do multiplication and then cast it back to slv. THe result contained 2's compliment number
thanks