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https://designers-guide.org/forum/YaBB.pl Design >> RF Design >> How to setup SepctreRF condition for whole PLL https://designers-guide.org/forum/YaBB.pl?num=1095406854 Message started by Wendy on Sep 17th, 2004, 12:40am |
Title: How to setup SepctreRF condition for whole PLL Post by Wendy on Sep 17th, 2004, 12:40am All, Can someone show me how to setup the SpectreRF simulation condition for a whole PLL to get the close loop phase noise? Is it simular as oscillator except deselecting the oscillator tap? Thanks, |
Title: Re: How to setup SepctreRF condition for whole PLL Post by Mighty Mouse on Sep 17th, 2004, 8:39am Check out section 1.2 (Direct Simulation) of http://www.designers-guide.com/Analysis/PLLnoise.pdf. You would not treat a PLL as a oscillator as there is a periodic input signal. Instead you treat it as a driven circuit. |
Title: Re: How to setup SepctreRF condition for whole PLL Post by Wendy on Sep 17th, 2004, 8:26pm Hi, MM, I read the paper, actually I already know that the setup for the close loop should be different from that for VCO. But what's the setup anyway? Would it be possible to let us know. Thanks. |
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