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Design Languages >> VHDL-AMS >> VDHL code for a boolean expression
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Message started by Mahesh on Oct 11^th, 2004, 10:50am

Title: VDHL code for a boolean expression
Post by Mahesh on Oct 11^th, 2004, 10:50am

Im new to vhdl and just want to learn the basics, ive come across a question and wanted to know how i would wrote the architechture statement, if anyone can help it would be great.

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x=(AC+BC+D) + BC

Title: Re: VDHL code for a boolean expression
Post by m4he5h on Oct 11^th, 2004, 11:03am

Thats mean to be

NOT (ac + NOT (B NOT C) + D) + NOT BC,
didnt come out right above

Title: Re: VDHL code for a boolean expression
Post by Paul on Oct 27^th, 2004, 8:55am

Mahesh,

have a look at the following page for some VHDL guidelines:
http://www.eda.org/rassp/vhdl

To write your expression, juste replace multiplication by AND and addition by OR and put brackets in the necessary cases.

Paul