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Design >> RF Design >> Transistor Layout
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Message started by logan on Oct 13^th, 2004, 1:18pm

Title: Transistor Layout
Post by logan on Oct 13^th, 2004, 1:18pm

I was told that the NMOS (or PMOS) transistor in my LNA design should be laid in roughly a square shape. I have not been able to find information elsewhere that confirmed this as a fact. Can someone confirm the optimum layout (Narrow/Broad/Square) and why.

Many Thanks

Title: Re: Transistor Layout
Post by Paul on Oct 27^th, 2004, 8:26am

Hello Logan,

you have to consider several aspects and decide which are most important to your design.

a) flicker noise is lower for wider W*L, i.e. function of 1/(W*L)
b) matching is proportional to 1/(W*L), but for very narrow or very short devices also to 1/W+1/L
c) with very short channels, you can experience velocity saturation, degrading the transconductance and increasing the channel thermal noise coefficient

I don't know if this fully answers your question...

Paul

Title: Re: Transistor Layout
Post by logan on Nov 12^th, 2004, 2:02pm

thanks paul. I think i know what you are talking about. We did have a visiting professor who told me that it should be square in shape as a rule of thumb. unfortuantely he visits us no more and no in-house experts in this field. so I am just feeling my way around things. I do have though another question which I shall also post at the top of the forum as a new topic

Q. is it not abnormal that I get a difference of 9 dB in losses between an ideal inductor and one from the model library ( i am using 3 metal cmos 0.35u) thanks