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Design Languages >> VHDL-AMS >> signal updating
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Message started by Mark Burford on Oct 19^th, 2004, 8:25am

Title: signal updating
Post by Mark Burford on Oct 19^th, 2004, 8:25am

I want to have a signal that updates from the quantity v across i through p1 to p2.

I have a process running also that I want the quantity in the sensitivity list, this is not allowed so I declared a signal ...
signal v_last : real;
v_last <= v;

v_last only seems to update once, no matter where I put the statement.

I want it to follow v.
Any ideas?

Thanks
Mark

Title: Re: signal updating
Post by Paul on Oct 27^th, 2004, 9:09am

Hi Mark,

I had to convert an analog signal into a digital one. I used a process sensitive to ana_sig'above(vth) in which I affected dig_sig to either '0' or '1'... I don't know if there is a more elegant way to do this, in case I am interested to learn.

In your case, you may try to write a process sensitive to
ana_sig'above(vth)
where vth is ana_sig(k-1)+ana_step

and ana_step will define your vertical tracking resolution (and so your simulation time).

Let me know if this works, I didn't try it.

Paul

Title: Re: signal updating
Post by Mark Burford on Feb 14^th, 2005, 10:22am

Hi Paul, thanks for feedback ages ago, I soved the problem, see code below:

;D

threshold <= not vs'above(v_last-delta_v) or vs'above(v_last+delta_v);

fdr_p1 : process (threshold) is
my process code
end process

v == expression dependant on stuff in process.

It allows good resolution and accuracy control. Ihad actually figured this before reading your response just now ages back.gtrea minds and all that!
Mark