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Design Languages >> Verilog-AMS >> Error encountered during NC Elaboration for config
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Message started by vivekrc on Oct 26^th, 2004, 2:19pm

Title: Error encountered during NC Elaboration for config
Post by vivekrc on Oct 26^th, 2004, 2:19pm

Hi,

I am getting this error and i dont know how to solve it.
ncelab:*internal*(rts_seghandler-SIGSEV unexpected violation pc =0x7f93310C addr=0X0)
This error occured when i was simulating my schematic design of current steering DACs in Cadence IBM 0.13 micron technology.
Design preparation was successfuly completed with no errors.
Thanks
Vivek

Title: Re: Error encountered during NC Elaboration for co
Post by Jon Sanders on Nov 20^th, 2004, 10:10am

Vivek, whenever you see an internal error it implies a bug. It might be you are trying to do something not support, or not officially supported yet but in any case internal errors mean Cadence did not account for the condition you gave it (whether it meant to or not).

So first please file a PCR if you have yet to do so. Outside of that you need to provide a bit more data for debugging. Some of the things that help are knowing where in Elab this failed which the log file often gives you clues to (especially if you have specified -mess). Did this fail before, during, or after discipline resolution? Depending on where it fails there are specific things to try.

If it failed prior to discipline resolution then something did not "hook" up correctly and try modifying your config where possible to see if you can find the block causing the problem. If you don't specify a default digital discipline you will see if it got to DR or not.

If it failed during discipline resolution try things like switching to detail resolution, forcing disciplines, checking for unique items in your design for proper hookup (iterated inst, wreal, digital net expressions, UDP, VHDL, ...).

It seldom failed after DR but when it does it likely issues with CM or Driver Receiver Segmentation. Here try different CM's just to see if that makes it work.

Of course similfying the design is also a helpful debugging tool since it allows you to find the problem area and easier to generate a testcase to be created that is free from your IP. But without data these are just guesses.

-jons

Title: Re: Error encountered during NC Elaboration for co
Post by Vivek Chandrasekhar on Nov 20^th, 2004, 11:50am

Hi Jon,

I didnot get this bug when i use ldv 5.1 instead of ldv 4.1. Cadence had bugs in the older version,so when i updated my version , i didnot get this segmentation fault.
thanks for your reply.
Vivek