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Design Languages >> Verilog-AMS >> Verilog-A model for VCO
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Message started by Rohan Batra on Nov 2^nd, 2004, 11:19pm

Title: Verilog-A model for VCO
Post by Rohan Batra on Nov 2^nd, 2004, 11:19pm

I am trying to write a verilog-A model for a VCO. But instead of the voltage out vs voltage in relationship, I want to model a frequency out vs voltage in relationship. Is there anyway to describe the output as a "frequency" discipline type. I know that you can declare something as a "voltage" or "phase" in verilog-A.

Title: Re: Verilog-A model for VCO
Post by sheldon on Dec 28^th, 2004, 4:46pm

Rohan,

Do it all the time, but I have always just output the
frequency as a voltage. Never actually seen anyone
create a separate discipline to do this. Have you tried
defining a new discipline for frequency in the discipline.vams,
(for Spectre) file? If you update the file you file, you need
to point to the correct one in module.

Best Regards,

Art Schaldenbrand

Title: Re: Verilog-A model for VCO
Post by Eugene on Jan 2^nd, 2005, 9:51pm

I also usually just represent frequency with a voltaqe. The trick is to choose the right frequency units (GHz, MHz, etc.) to keep numbers reasonable. I use voltage primarily because that node is a convenient place to insert a zero-voltage DC voltage source, with AC magnitude=1, to compute loop gain. I think you will have to create a Verilog A module for this source if you use a frequency discipline. However, if you use voltage, you can use the Spectre primitive. Another reason I usually choose the electrical discipline is that, being an electrical engineer, it is often easier for me to introduce filters using RLCs instead of creating another verilogA block for a Laplace transform. I also wonder if the simulation runs faster with primitives instead of Laplace blocks.

Title: Re: Verilog-A model for VCO
Post by gogomi on Feb 28^th, 2005, 9:42pm

Hi,

Just wondering if you use voltage to represent frequency, then how do you model the phase?
Do you also use voltage?

gogomi