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https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> How to simulate clock jitter? https://designers-guide.org/forum/YaBB.pl?num=1101003894 Message started by jimmy on Nov 20th, 2004, 6:24pm |
Title: How to simulate clock jitter? Post by jimmy on Nov 20th, 2004, 6:24pm Hi all, I have a quesiton on how to simulate jitter? I want to simulate the clock jitter from my clock generation circuit. Say, if I apply a ideal sinewave to my clock generation circuit, I will get a clock signal after a few digital gates. All device noise, supply nose and substrate noise will add jitter noise to the final output. I want to simulate how much jitter my final clock have. Can any one tell me how to do this simulation? thank you so much, jimmy li |
Title: Re: How to simulate clock jitter? Post by Andrew Beckett on Nov 21st, 2004, 10:16pm There are a few papers on this site about analysing phase noise and jitter in PLLs; the same approaches could be used for your circuit, I'm sure. Also, spectreRF in IC5141 has a new mode in pnoise analysis to specifically measure jitter in both driven and autonomous systems. You might want to try that? Regards, Andrew. |
Title: Re: How to simulate clock jitter? Post by jimmy on Nov 22nd, 2004, 8:00pm Andrew: My circuit is driven by a peridical signal, not like VCO. I choose "time domain" for "Noise type" in PNOISE form and then simulate the voltage noise at the zero-crossing poiint. After simulation, I can plot the spectrum at the zero-crossing point of my output clock. Then I do integration to get the noise power. The time jitter at the zero-crossing point equals to the noise power divided by the square of slew-rate at the zero-crossing point. Do you think I am right or wrong? Thank you so much for your help, jimmy li |
Title: Re: How to simulate clock jitter? Post by Frank Wiedmann on Nov 22nd, 2004, 11:49pm You are almost right. Please take a look at the thread starting at http://www.designers-guide.com/Forum/?board=rfsim;action=display;num=1092399689;start=0, where I explain the procedure in some detail. Please note that the thread is distributed over several pages, the most interesting stuff is probably on page 2. |
Title: Re: How to simulate clock jitter? Post by jimmy on Nov 23rd, 2004, 2:36pm Frank, Thank you, I have read your replies. They are very useful to me. I also have read the two documents on the website and got more sense. Now I still have some small questions. Hopefully you can give me a hand. 1. You said PSS simulation can find tc.I used transient to do this and found these two simulations show different result. I mean, the zero-crossing point of my output clock are different from these two simulations. I don't know why. And as you said, tc is"the time where the signal crosses the theshold level of the following stage", so do you think I shouldn't use zero-crossing point as tc? Do you think I should connect the following stage to my clock otherwise I can't find tc? I think the sizing of the following stage will affect tc value. 2. In the direct plot form, when I chose tdnoise/integ output noise/total noise/spectrum/magnitude, I didn't see any fields allowing me to input starting and ending frequencies. When I clicked "plot" then, I got an error message "fprint/sprintf: format spec incompatible with data nil". I don't know why. The cadnece i am using is 5.0.0_MSR 3. If I chose 'output noise", not "integ output noise", I got the spectrum after clicking plot. The unit of Y-axis is V/sqrt(Hz). Do you mean I should integrate this curve from 0 to Fs/2? I think the result will be different than if I integrate power then take square root. I mean, integ(V) is not equal to sqrt (integ(Power)), am I wrong? I am a little confused here on the equation (53) and (54) in document "predicing the phase noise dn jitter of PLL....". 4. Since the jitter is in the order of ps, Do you think the tc I used should be accurate enough, for example, 21.12345n, not just 21.1n? And do you think tc should be within 0 and T. I found PSS only generata a transient waveform from 0 to T thank you so much, jimmy li |
Title: Re: How to simulate clock jitter? Post by Frank Wiedmann on Nov 24th, 2004, 12:08am Quote:
You have to use the PSS simulation to find tc, because the PSS simulation is used as the basis for the following PNOISE analysis. The timepoint tc is where you want to examine the jitter of your circuit. If you have a differential circuit, the zero-crossing point will probably be ok. Quote:
I'm afraid I can't help you with problems you have with your specific Cadence installation. You should probably ask your local experts to examine these problems. Quote:
With noise, you always have to integrate the power. So, if you have the result in V/sqrt(Hz), you first have to square it in order to get the power, then integrate the power, and finally take the square root to get the "noise amplitude" in volts. Quote:
This depends on your circuit. You can just try and see if it makes any difference. With PSS, the time will always be between 0 and T. |
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