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Simulators >> Circuit Simulators >> SPICE simulation time and model
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Message started by ywguo on Nov 24^th, 2004, 12:38am

Title: SPICE simulation time and model
Post by ywguo on Nov 24^th, 2004, 12:38am

Hi,

I am curious about the big difference between the simulation speed for two similar circuits. Would you please help me?

I have been redesigning a circuit using 0.25um CMOS technology. The original circuit was implemented using 0.35um CMOS technology.

The design has two oscillators, one very fast (~1GHz), the other slow (~1MHz for the original design, ~4MHz for the new design). So it takes so long time to run the transient simulation for both design.

But I am curious that the simulation time for the new design is much longer than that for the original design though both circuits has similar structure and spec.

It took near 300,000 seconds to run a 500us transient simulation using SPICE option method=gear. But it took more than 450,000 seconds to run just a 50us transient simulation using default integration method (trapzoid). As well known, transient simuation is much slower if using gear method. :( So it makes me deep confused.

The detail statistics is shown below.

For the original design.
analysis time # points tot. iter conv.iter
transient 291621.51 500001 81511395 22966268 rev=******

For the new design.
analysis time # points tot. iter conv.iter
transient 409348.59 5001 45405049 12645293 rev=******

From the above data, the convergent iteration of the new design is about half of that of the original design. But remember it is a 500us transient simulation for the original design, and just a 50us transient simulation for the new design. That means the average internal time step is about 1/5 of that for the orignal design.

What makes the simulation for the new design interated so much times? And its internal time step smaller?

I notice one difference between the SPICE models for 0.35um and 0.25um. The SPICE model for 0.35um has a non-zero HDIF parameter(hdif=3.5e-7), but HDIF=0.0 for the 0.25um SPICE model. I suspect that will deteriorate the discontinuity of the 0.25um SPICE model. Thus SPICE tool need smaller internal time step and much more iteration.

I am not an expert in SPICE algorithm and MOS model. So I need your help!

What do you think the reason? Do you have any advise to speed the simulation?

Thanks
Yawei

Title: Re: SPICE simulation time and model
Post by August West on Nov 24^th, 2004, 8:36am

Yawei,
Your circuit is probably experiencing 'trapezoidal ringing'. You can generally confirm this by looking at the waveforms for the power supply currents. Trapezoidal ringing is occuring when the waveform alternates between being too high and too low on successive time points. To avoid it, switch to Gear.

This condition is well described in Kundert's book: "The Designer's Guide to Spice and Spectre". Look at the section on 'Ringing" starting on page 150. This book is very good for answering these types of questions. Anyone running Spice should own a copy. You can find more information about it at http://www.designers-guide.com/Books/dg-spice/index.html.

-August

Title: Re: SPICE simulation time and model
Post by ywguo on Nov 28^th, 2004, 5:32pm

Hi, August,

I modified the 0.25um SPICE model a little, assigned HDIF=2.5e-007, ACM=12. Now I am running a 200us transient simulation. The simulation speed almost doubles. So I think the model must have impacted the iteration and time step.

But it is still much slower than the simulation for 0.35um design. I will try method=gear following your advise.

Thanks very much.
Yawei

Title: Re: SPICE simulation time and model
Post by ywguo on Nov 29^th, 2004, 6:36pm

Hi, August,

I checked the power supply current, it had very high frequency noise of several micro Ampere. I think that is trapzoidal ringing because it cannot be related to any behavior of that circuit.

So I run the simulation again with method = gear. To my disappointment, the ringing still exists, even not reduce. :( It is strange as normally the trapzoidal ringing always disappear when the method is set to grear. The simulation speed decreases to one half, too.

Now I am runing a simulation using smaller transient step and method = gear.
.tran 1ns 50us
I found the simulation speed almost doubles than method = gear and 10ns step. It really confuses me.

Thanks

Yawei

Title: Re: SPICE simulation time and model
Post by August West on Nov 30^th, 2004, 8:06am

Trapezoidal ringing is always "point-to-point" ringing (alternating between too high and too low). If it is not point-to-point ringing, or if it becomes smooth ringing as you tighten tolerances, or if it remains when not using trapezoidal, it is not trapezoidal ringing.

If it is not trapezoidal ringing, it must be your circuit itself. The reason why your simulations run so slowly is because it exhibits a parasitic oscillation or highly underdamped behavior.

-August

Title: Re: SPICE simulation time and model
Post by Geoffrey_Coram on Jan 10^th, 2005, 2:30pm

Note that HDIF is used to compute AD, AS, PD, PS, which are used for junction capacitances. The foundry may have expected you to use layout-extracted values for these parameters, in which case HDIF is not necessary.

Obviously, these capacitances can smooth out the circuit response; I'm not sure if this is what you meant by "deteriorate the discontinuity of the 0.25um SPICE model."