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Design >> High-Speed I/O Design >> deadzone in PLLs
https://designers-guide.org/forum/YaBB.pl?num=1101349423

Message started by velan on Nov 24^th, 2004, 6:23pm

Title: deadzone in PLLs
Post by velan on Nov 24^th, 2004, 6:23pm

its mentioned in literature that dead zone is undesirable in PLLs.. .. but is there a way to introduce dead zone in PFDs, the size of which is controllable .. I cud think of slowing down the switches of the chargepump than the critical reset path ... is there any other way ?

Title: Re: deadzone in PLLs
Post by s.venkatareddy on Jan 31^st, 2005, 9:16pm

dead zone is caused due to pfd ckty.thats the only method avaliable till now.having deadzone has both advantages and disadvantages.
i think i am clr to u problem

Title: Re: deadzone in PLLs
Post by Frank Wiedmann on Jan 31^st, 2005, 11:17pm

See http://www.designers-guide.com/Forum/?board=ms_design;action=display;num=1085897049.