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Design >> Mixed-Signal Design >> PAC analysis of "Gain Stage"
https://designers-guide.org/forum/YaBB.pl?num=1101544899

Message started by behzad on Nov 27^th, 2004, 12:41am

Title: PAC analysis of "Gain Stage"
Post by behzad on Nov 27^th, 2004, 12:41am

Hello all,
I want to simulate a 1.5 bit gain stage by PAC.
I have already done the PAC analysis for SC integrator and it works right.
But since in SC gain stage there is a reseting phase in the output, PAC result shows the gain 6dB less than real number.
Is this due to PAC analysis limitation or there is somethin wrong in my simulation?

Regards
Behzad

Title: Re: PAC analysis of "Gain Stage"
Post by August West on Nov 29^th, 2004, 9:14am

PAC is considering the whole signal (over a complete clock cycle) when computing the gain. If your signal spends half its time at zero due to a reset phase, that will effectivly reduce your gain by half (6 dB).

To avoid this problem, use the idealized sample-and-hold given in http://www.designers-guide.com/Analysis/hidden-state.pdf and sample the output of you circuit at the time the subsequent stage would normally sample it. Then have PAC compute the transfer function to the output of the sample and hold. This gives a much better measure of the effective gain of you stage, though it does add some sin(x)/x distortion.

-August