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Design Languages >> Verilog-AMS >> AHDL (verilog-A) model
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Message started by jimmy on Dec 1^st, 2004, 12:48pm

Title: AHDL (verilog-A) model
Post by jimmy on Dec 1^st, 2004, 12:48pm

Hi,

I found Verilog-A or AHDL models from ahdlLib all resets their outputs to zero at begining. Can I turn off this resetting?

thanks,
jimmy

Title: Re: AHDL (verilog-A) model
Post by Andrew Beckett on Dec 1^st, 2004, 10:01pm

This isn't true for all components in ahdlLib. Not all outputs will be zero at time zero. It depends on the DC solution.

Yes, they will probably start at 0 when trying to find the DC solution (but then so does every node in the circuit).

Without some specifics it's impossible to answer your question. It may be that the code needs modifying to do something different on an @initial_step or it may be that you need to do a nodeset, or it could be something completely
different altogether.

Please ask a more specific question, with an example, perhaps?

Regards,

Andrew.