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Design Languages >> Verilog-AMS >> compiling error
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Message started by ppm on Dec 3^rd, 2004, 12:02pm

Title: compiling error
Post by ppm on Dec 3^rd, 2004, 12:02pm

Can someone help me correct the error below:

ground gnd;

I have "illegal ground node 'gnd' " error with the above statement? I read from Ken's paper, PLLnoise.pdf, that "this ground statement is not currently supported in Cadence's Verilog-A implementation, so instead ground should be explicitly passed into the model through a terminal. "

How do I do that??? Help please?!?

ppm

Title: Re: compiling error
Post by Ken Kundert on Dec 3^rd, 2004, 2:04pm

Add it as a terminal of the module and pass it in from the top level.

-Ken