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Design >> Analog Design >> Phase Margin versus Load Capacitance
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Message started by OpAmp on Dec 11^th, 2004, 10:38am

Title: Phase Margin versus Load Capacitance
Post by OpAmp on Dec 11^th, 2004, 10:38am

Hi,

I am going to sweep the load capacitance of my designed op-amp and see the corresponding phase margin. Actually, I need a plot for phase margin versus load capacitance.

Can anybody help me how to do it with Spectre?

Thanks in advance.

Title: Re: Phase Margin versus Load Capacitance
Post by Andrew Beckett on Dec 12^th, 2004, 12:46am

With the analog design environment (aka AnalogArtist) this
is easily achieved. You can either use the stb (stability) analysis added in the IC50 release, which will measure the phaseMargin and gainMargin (and loop gain) of a loop - the loop can stay closed; you just need to put an iprobe in the loop, and then point the stb analysis at that iprobe. Or you can use one of the traditional methods (ac analysis of the amp in open loop, probably getting the operating point from a closed loop simulation, using the spt1switch etc component in analogLib to open/close in different analyses; or using Middlebrook's method) - and use the phaseMargin function in the calculator.

Having got your appropriate output expression ready for a single point, then do a parametric sweep of the load capacitance (make it a design variable). What ADE will do is plot any scalar value against the swept variable, giving you what you want.

This isn't an absolutely detailed step by step answer, because that would take quite a lot of time, and probably I'd need to do it to make sure I got the description spot on - I'm assuming you have a reasonable idea how to use the tools.

Regards,

Andrew.

Title: Re: Phase Margin versus Load Capacitance
Post by uncle_ezra on Dec 14^th, 2004, 9:23pm

So for stb analysis, you put a voltage source with 1V AC magnitude between between the node that you want to break and probe it in the analysis. Is that right? It seems to work, but want to confirm.

Thanks

Title: Re: Phase Margin versus Load Capacitance
Post by Andrew Beckett on Dec 14^th, 2004, 10:02pm

Yes, that would work. However, the 1V AC magnitude is not necessary (it doesn't do anything). Essentially you have to have a device for measuring the current in the loop - and that would be either a zero-volt vsource or an iprobe.

Regards,

Andrew.

Title: Re: Phase Margin versus Load Capacitance
Post by uncle_ezra on Dec 19^th, 2004, 5:03pm

Yep it works ! Now I have another question, what if I have a fully differential amplifier how do I simulate Loop Gain?

Thanks

Title: Re: Phase Margin versus Load Capacitance
Post by sheldon on Dec 19^th, 2004, 6:21pm

Hi,

See Ken's book, "The Designer's Guide to SPICE and
Spectre" pages 113-128. The explanation includes
techniques for measuring both differential and common-
mode loop characteristics. In addition, you can check out
the following link:

http://engr.smu.edu/orgs/ssc/slides/20001215b.pdf

Sheldon