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Design Languages >> Verilog-AMS >> SNR of an ideal ADC
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Message started by Vivek Chandrasekhar on Dec 11^th, 2004, 1:35pm

Title: SNR of an ideal ADC
Post by Vivek Chandrasekhar on Dec 11^th, 2004, 1:35pm

Hi,
Digital output of an ideal 4 bit ADC was computed using Verilog AMS.This digital output was stored in a .dat file.
I calculated SNR of this ideal 4 bit ADC using Matlab code . My SNR value of 18dB doesnot seem to match the ideal value of (1.76+6.02n where n is resolution of ADC) 25.78dB for a 4 bit ADC. I am using a sampling frequency of 2.5 GHz and input frequency of 500MHz.
I would be greatful to anyone who could help me solve this problem.
Thanks
Vivek

Title: Re: SNR of an ideal ADC
Post by sheldon on Dec 28^th, 2004, 4:40pm

Vivek,

Simulating ADC dynamic performance is non-trivial. The
results are dependent on the setup of the simulation. You
will need to use the same methodology that designers use
when testing data converters on the bench. The best place
to look for information is AD/Maxim/BB. You will need to
search for information on coherent sampling. Here is one
useful link from Maxim,

http://japan.maxim-ic.com/tools/calculators/index.cfm/calc_id/appnote3190

To summarize the issues, you need to do two things:

1) Control the time span used for the FFT data record so
that it contains an integer number of periods of the
clock and input signal. This will eliminate spectral
leakage so you won't need to use windowing functions.

NOTE: Everybody uses windowing function on the testbench.
It can't be helped since it is impossible to perfectly
synchronize the clock and input. However, it can be helped
when simulating so don't do it! Windowing functions can
mask the actualy characteristics of the ADC.

2) Make the ratio of the input signal to the clock signal ,
depend on the prime number for example. 17 periods of
the input to 256 periods of the output. If you use even
numbers, for example, 1MHz input for a 10MHz, sample
rate, then the noise shows up at the harmonics of the
beat frequency, e.g., 2MHz, 3MHz, ...
So the SNR will be correct but the SFDR will be incorrect.

3) The simulation you are performing only inlcudes the
quantitazation noise of the ADC, so you should see
the SNR match the ideal value. I have checked this
for 10 bit ADCs and the theory matches simulations.

Best Regards,

Art Schaldenbrand

Title: Re: SNR of an ideal ADC
Post by sheldon on Jan 1^st, 2005, 7:28pm

Vivek,

Just wanted to add a little more for your specific case.
1) Choose an input level just below the full scale input. For
example, if the full scale input is 1Vpp, the typical input
level is -1dBfs, 1 dB below full scale, or 0.89125V. The
signal needs to be large enough so that you measure the
full dynamic range, but not so large that you overload the
the ADC. Or you need to compensate for the input level,
that is, if the input is -6dBfs, then the actual SNR should
be 6dB greater than the measured SNR(ideally).

2) For your case assuming a 256 point FFT, you need to
run a simulation that is 256 * ( 1 / 2.5e9) = 102.4ns +
alpha, alpha allows start-up transients to to settle and
selecting the correct point in the sampling period for
the FFT.

3) You need to offset the data points in the FFT so that
the reconstructed analog has settled to its final value.
For example, allowing 1 period to settling startup
transients and 390 ns, sampling period is 400ns, for
the analog to settle, then the first time should be
790ns for the FFT and the transient simulation should
be at least 103.19ns long.

4) For a sampling frequency of 2.5GHz, a target input
frequency of 500MHz, and a 256 point FFT, the input
frequency should be something like 47/256 * 2.5GHz,
or 458.984375MHz.

Best Regards,

Sheldon