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Design Languages >> Verilog-AMS >> Named Port Association in Verilog-AMS
https://designers-guide.org/forum/YaBB.pl?num=1103442432

Message started by Vikram Srinivasan on Dec 18^th, 2004, 11:47pm

Title: Named Port Association in Verilog-AMS
Post by Vikram Srinivasan on Dec 18^th, 2004, 11:47pm

Hi

I was designing an RC network and I decided to have 3 modules in my source file-2 for definitions of the resistor and capacitor and the main module where instances of the R and C were created(with the appropriate interconnection). This is the code I wrote:

module rescap(posr,negc);
electrical posr,negr,negc;
resistor res(.p(posr),.n(negr));
capacitor cap(.pos(negr),.neg(negc));
endmodule

module resistor(p,n);
parameter real rn=1k from [1:inf];
electrical p,n;
analog
begin
V(p,n) <+ rn*I(p,n);
end
endmodule

module capacitor(pos,neg);
parameter real c=100 from [1:inf];
electrical pos,neg;
analog
begin
I(pos,neg) <+ c*ddt(V(pos,neg));
end
endmodule

My test bench file looks like this:
module rctest(posr,negc);
electrical posr,negc;
wire negr;
resistor #(.rn(1000)) res(p,n);
capacitor #(.c(100)) cap(pos,neg);
vsource #(.type("sine"),.dc(0),.ampl(5),.freq(5000)) vin(posr,negc);
endmodule

Now when I compile this, I get an error message that "Named Port Association is not valid for analog primitives in Affirma-AMS". I am confused. I thought named port association was valid in V-AMS.

Am I missing something?

Title: Re: Named Port Association in Verilog-AMS
Post by Mighty Mouse on Dec 20^th, 2004, 9:58am

Named port associations seem like they should work. Kundert included an example of it in his book (see listing15 in chapter 4 at http://www.designers-guide.com/Books/dg-vams/index.html), and he claims they were all tested in AMS-Designer. Perhaps the fact that you have chosen names for your modules that are exactly the same names used for the built-in primitives is confusing things. Try myres rather than resistor, etc.

- MM -

Title: Re: Named Port Association in Verilog-AMS
Post by Vikram Srinivasan on Dec 20^th, 2004, 11:15am

Thanks MightyMouse !! I'l try that !