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Design Languages >> Verilog-AMS >> Voltage Source Definition
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Message started by Vikram Srinivasan on Dec 23^rd, 2004, 4:47pm

Title: Voltage Source Definition
Post by Vikram Srinivasan on Dec 23^rd, 2004, 4:47pm

Hi

I am trying to have 3 voltage sources in my testbench:

vsource #(.type("sine"),.dc(0),.freq(5000),.ampl(5)) vin1(vinp,vss);
vsource #(.type("dc"),.val(2.5)) vin2(vinm,vss);
vsource #(.type("dc"),.val(5)) vin3(vdd);

Now is this a proper definition for a DC source?Am I allowed to have such multiple definitions in a single test bench(they are for the Positive,Negative and High Voltage State terminals of an op-amp with vss being grounded)

what parameters should I specify for a dc source?