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Design >> Mixed-Signal Design >> Digital PLL jitter reduction
https://designers-guide.org/forum/YaBB.pl?num=1105300152

Message started by mark on Jan 9^th, 2005, 11:49am

Title: Digital PLL jitter reduction
Post by mark on Jan 9^th, 2005, 11:49am

I was wondering if anyone knew of a good method to reduce the peak to peak jitter of a digital PLL beyond the cycle time of the base clock that drives the DCO. I think that interpolation or some sort of analog filtering may do the trick. However, these may be difficult blocks. Does anyone know of any good papers that outline methods to acheive this jitter reduction.
Thanks