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Design >> Mixed-Signal Design >> Simulation and plot of switch on-resistance
https://designers-guide.org/forum/YaBB.pl?num=1105907467

Message started by JJ on Jan 16^th, 2005, 12:31pm

Title: Simulation and plot of switch on-resistance
Post by JJ on Jan 16^th, 2005, 12:31pm

Hello folks. Very nice to find such a great forum.

I am using Cadence to design a switched-capacitor circuit. I am wondering how to simulate the CMOS switch on-resistance and plot it against Vgs -Vth for fixed devices size. Could anyone show me the way? Thanks a lot in advance.

Title: Re: Simulation and plot of switch on-resistance
Post by ywguo on Jan 16^th, 2005, 9:17pm

Hi, JJ,

I plot on-resistance of MOS switch using the following card in SPICE.

.probe ron=par('(v(in)-v(out))/I1(MS)')

where ron is the on-resistance of MOS swtich. v(in) and v(out) is input voltage and output voltage of that switch, respectively. MS is the MOS switch.

Make your MOS switch in normal operating mode and run a transient simulation.

Good luck

Yawei

Title: Re: Simulation and plot of switch on-resistance
Post by boa on Jan 18^th, 2005, 3:58pm

This thread might be helpful to you:

http://www.designers-guide.com/Forum/?board=analog_design;action=display;num=1076363657;start=0#0