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Modeling >> Semiconductor Devices >> MOSFET non-linear operation for VDS_DC=0.
https://designers-guide.org/forum/YaBB.pl?num=1106162870

Message started by Fernando_Rangel on Jan 19^th, 2005, 11:27am

Title: MOSFET non-linear operation for VDS_DC=0.
Post by Fernando_Rangel on Jan 19^th, 2005, 11:27am

Hello,

I have to use a MOSFET operanting when the drain-source DC voltage is zero. VGS is chosen to be just a little higher than Vt.
Normally, the MOSFET in this case would be in the lienar region, however, as we observed from measures of Ids when Vds is about some hundreds of microvolts @ 2.4 GHz, there are a very big DC component. This means that there are a great distortion here, not predicted by common foundry models.

Does anyone have a clue about the MOSFET behavior under the circustances mentioned above ?

Thanks in advance.

Fernando

Title: Re: MOSFET non-linear operation for VDS_DC=0.
Post by Kevin Gard on Apr 3^rd, 2005, 8:20pm

There is a good conference paper on the topic from CICC 2004
RF distortion analysis with compact MOSFET models
Bendix, P.; Rakers, P.; Wagh, P.; Lemaitre, L.; Grabinski, W.; McAndrew, C.C.; Gu, X.; Gildenblat, G.;
Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004
3-6 Oct. 2004 Page(s):9 - 12

The basic answer is that the equations used to model velocity saturation for short channel devices may not have higher order derivatives at Vds=0V. In some models, this expression may have a singularity at Vds=0.

In the past, some engineers have used a small current source to force a small vds when using a floating fet.

Title: Re: MOSFET non-linear operation for VDS_DC=0.
Post by Geoffrey_Coram on Jun 6^th, 2005, 8:22am

Fernando -
Are you saying you are *measuring* a distortion? The paper Kevin cites shows why simulations erroneously predict distortion near Vds=0 because of poor formulation of the symmetry (drain-source swapping).