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Design Languages >> VHDL-AMS >> clock multiplier
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Message started by jr81 on Jan 25^th, 2005, 5:22am

Title: clock multiplier
Post by jr81 on Jan 25^th, 2005, 5:22am

Hi,

I am trying to generate a clock multiplier in VHDL. I have successfully written a clock divider using a counter but I was wondering if anyone could point me in the right direction to design a clock multiplier.

Thanking all in advance

Title: Re: clock multiplier
Post by Paul on Jan 28^th, 2005, 3:09am

Hello,

as far as I know, you cannot synthesize a clock multiplier. The clock multiplier closest to "standard" digital design is based on a DLL where you select the outputs of each delay cell one after the other. Most clock multipliers are either based on this technique or on phase-locked loops (PLL).

Paul