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Design Languages >> Verilog-AMS >> Op-Amp code and Ramp Input
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Message started by Vikram Srinivasan on Jan 27^th, 2005, 3:03pm

Title: Op-Amp code and Ramp Input
Post by Vikram Srinivasan on Jan 27^th, 2005, 3:03pm

Has anybody worked with a Verilog-AMS code for an op-amp?Can you share it with me?I have the one posted on this website , but I dont follow it entirely.

And how does one define a ramp(steadily increasing )dc input for a voltage source?

Vikram

Title: Re: Op-Amp code and Ramp Input
Post by Andrew Beckett on Jan 28^th, 2005, 10:35pm

First question - try ahdlLib (in the IC installation - e.g. IC5033, IC5141 etc) in:

<instdir>/tools/dfII/samples/artist/ahdlLib

There is an "opamp" model there.

You can also use the "modelwriter" tool to create an opamp verilog-a model.

Second question is answered in http://www.designers-guide.com/Forum/?board=verilogams;action=display;num=1105061995;start=0#9

Title: Re: Op-Amp code and Ramp Input
Post by Vikram Srinivasan on Feb 20^th, 2005, 6:43pm

Hi Andrew

I have been using the op-amp model from the Cadence library. The amplification behavior is however not clear.

For instance,I built a voltage follower circuit to test the functionality of the model. Therefore, I used the code EXACTLY in the way it was in the cadence folder and I fed the output to the -ve terminal while giving a 1v dc source to the +ve terminal.

I find that the output is not equal to the input, it is infact ~3.05V; 3 times the input...I have not included any other elements here.

Title: Re: Op-Amp code and Ramp Input
Post by Andrew Beckett on Feb 20^th, 2005, 10:09pm

Vikram,

I did not see that behaviour. Did you wire it up correctly?

Here's my netlist:

Code:

// Generated for: spectre
// Generated on: Feb 21 06:03:48 2005
// Design library name: test
// Design cell name: testopamp
// Design view name: schematic
simulator lang=spectre
global 0

// Library name: test
// Cell name: testopamp
// View name: schematic
R0 (op 0) resistor r=1K
VREF (ref 0) vsource dc=1.5 type=dc
VDD (vdd 0) vsource dc=3 type=dc
V0 (inp 0) vsource dc=1 type=dc
I0 (op ref inp op vdd 0) opamp
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 ckptclock=1800 \
sensfile="../psf/sens.output" checklimitdest=psf
dcOp dc write="spectre.dc" maxiters=150 maxsteps=10000 annotate=status
dcOpInfo info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
saveOptions options save=allpub
ahdl_include "/cds/hppa/IC5141_hot/tools.hppa/dfII/samples/artist/ahdlLib/opamp/veriloga/veriloga.va"

Note that originally I had the VREF source set to 0V, and I changed the 1.5V to see if that had an effect (it didn't). In my case the output was at 1V, as expected.

Regards,

Andrew.

Title: Re: Op-Amp code and Ramp Input
Post by Vikram Srinivasan on Feb 21^st, 2005, 8:44pm

Hi Andrew

The following is my test bench for the voltage follower.As you can see, I tried creating a branch named "follow" between vout and vin_n. I have not created any other instances or made any other connections. I am giving a 1V dc to vin_p and supplyvoltages to vspply_p and vspply_n...

I see 1V at vin_p and vin_n. But for vout, I see a spike from 0V to 5V which quickly stabilises to ~3.05V...

Is this branch connection valid for the feedback?I tried defining

wire vin_n,vout;

But this gave me an invalid declaration error.

`include "disciplines.vams"
`timescale 10ps/1ps

module opampfollower(vout,vref,vin_p,vin_n,vspply_p,vspply_n);

inout vout,vref,vin_p,vin_n,vspply_p,vspply_n;
electrical vref,vout,vin_p,vin_n,vspply_p,vspply_n;
ground vref;

opamp opamp (vout,vref,vin_p,vin_n,vspply_p,vspply_n);
branch(vout,vin_n) follow;

vsource #(.type("dc"),.dc(1)) vin1(vin_p,vref);
vsource #(.type("dc"),.dc(2.5))vin2(vspply_p,vref);
vsource #(.type("dc"),.dc(-2.5))vin3(vspply_n,vref);

endmodule

Unfortunately, I am using SimVision and I'm unable to compare my simulation to the Spectre output(although I understood what your pasted code described).

Thank you

Vikram

Title: Re: Op-Amp code and Ramp Input
Post by Andrew Beckett on Feb 21^st, 2005, 9:37pm

Vikram,

Your loop isn't closed. Simply defining a branch between vout and vin_n doesn't close the loop - it just defines a named branch that you can then use in the Verilog-AMS code.

If you add:

Code:

analog V(follow) <+ 0;

then that would solve the problem. Or, you could remove the branch and do:

Code:

analog V(vout,vin_n) <+ 0;

Or, more simply, you could change the opamp instance to:

Code:

opamp opamp (vout,vref,vin_p,vout,vspply_p,vspply_n);

i.e. change the vin_n connection to be vout.

Or you could have put another vsource in to close the loop.

Doing any of these things solves the problem.

If you'd entered a schematic and run AMS Designer through the environment, I'm sure you'd not have had a problem, because it would have been easy to connect up.

Alternatively, you should read the documentation carefully. I'd also recommend Ken and Olaf's book http://www.designers-guide.com/Books/#Kundert-2004 to learn basics like this.

Regards,

Andrew.

Title: Re: Op-Amp code and Ramp Input
Post by Vikram Srinivasan on Feb 23^rd, 2005, 6:44pm

Hi Andrew

Well,I knew I could solve the problem by adding a source at vin_n as well as by creating an instance with 'vout' instead of 'vin_n'...but I wanted to know why the model didnt work with a branch.

Thanks very much for providing a list of options....I dont have access to Olaf and Kundert's book(although I need it badly)...that explains why I still have elementary questions propping up !!!

Thanks again

Vikram

Title: Re: Op-Amp code and Ramp Input
Post by Ken Kundert on Feb 23^rd, 2005, 8:58pm

When you added the branch statement, you declared a branch, but you never described the branch. With no behavior described for the branch, Verilog-AMS defaults the branch to pass zero current. What you want is that there be no voltage across the branch. Thus, you have to add the statement that Andrew suggested ...

Code:

analog V(follow) <+ 0;

-Ken

Title: Re: Op-Amp code and Ramp Input
Post by Vikram Srinivasan on Feb 24^th, 2005, 11:37am

Hey

Thanks Ken!I understand what I should be doing with branches now. This forum is a life-saver!

Vikram

Title: Re: Op-Amp code and Ramp Input
Post by jk on Apr 3^rd, 2006, 5:51pm

Hi Andrew,

I am also looking for a code for an OP-Amp(non ideal)
I am new to the forum and dont know how I should use the path you suggested to get the model -- pls suggest
Also Vikra, could you pls attach the cadence model that you mentioned.

Thanks a lot ...

Title: Re: Op-Amp code and Ramp Input
Post by Andrew Beckett on Apr 3^rd, 2006, 10:57pm

The path I gave was to the ahdlLib library within the Cadence installation. If you add:

Code:

DEFINE ahdlLib $CDS_INST_DIR/tools/dfII/samples/artist/ahdlLib
DEFINE bmslib $CDS_INST_DIR/tools/dfII/samples/artist/bmslib

to your cds.lib file, you'll see these libraries within DFII.

You can also use the modelwriter tool to create behavioural models (just type modelwriter in a terminal window), and there's a model there for a non-ideal opamp.

There are also models at:

http://www.designers-guide.org/VerilogAMS/

That's the Verilog-AMS link at the top of the page... don't think there's a non-ideal opamp there though.

Regards,

Andrew.

Title: Re: Op-Amp code and Ramp Input
Post by jk on Apr 4^th, 2006, 6:54pm

Thanks a lot Andrew! This site is blessing ..especilally for novices like me :)

Title: Re: Op-Amp code and Ramp Input
Post by jk on Apr 11^th, 2006, 11:54am

hi andrew,
Could you also tell me the textual reference of the Behavioural model (for non ideal OPamp) in the cadence ahdllibrary?
I am trying to understant the model but cant relate it to nay of the models i have come accress.

Also, I am having difficulties writing test benches/ stimulus for the OPamp (I want to try it in different closed loop configurations)
Could you point me to some examples or tutorials that would be able to help

Thanks again,
jk

Title: Re: Op-Amp code and Ramp Input
Post by Andrew Beckett on Apr 11^th, 2006, 9:57pm

I don't understand what you mean by the "textual reference of the Behavioural model...".

As for tutorials for op-amp testbenches, I'd say that your best bet is to look in any books on op-amp design (e.g. Gray and Meyer, Allen and Holberg, Gregorian and Temes, etc - see http://www.designers-guide.org/Books).

Andrew.

Title: Re: Op-Amp code and Ramp Input
Post by jk on Apr 13^th, 2006, 3:34pm

Hi Andrew,

What I mean is, is there any place where this model is described? As in a spec or document gives
more info about the INSTANCE parameters .

From the looks of it, I am not very clear of how this OPamp is modeled. So I need hlep in understanding it.

Thanks again
Jyoti

Title: Re: Op-Amp code and Ramp Input
Post by Andrew Beckett on Apr 20^th, 2006, 12:30pm

The best place is in the comments at the top of the code. It may be in a manual in cdsdoc, but I don't recall whether it is or not for these manuals.

Similarly the models produced by modelwriter are pretty well commented.

Regards,

Andrew.

Title: Re: Op-Amp code and Ramp Input
Post by jbdavid on Apr 21^st, 2006, 1:43am

Most of the folks I know that use the model just look at the comments in the code to make the understanding.. but of course most of them STARTED with opamp macro models in spice.. (probably showing my age) so we don't need more..

Basics - first stage sets the gain, accounts for input saturation.
second stage sets the dominant pole
output stage takes into account the supply clamping, output loading (by way of feedback to the second stage)

This is off the top of my head.. hopefully others can expand on this..

its (or something quite similar) is probably described in Miller and Fitzpatrick as well... but this was probably not copied from that ..