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Design Languages >> Verilog-AMS >> The D flip-flop model looks like a latch ??
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Message started by jimi on Feb 1^st, 2005, 11:34pm

Title: The D flip-flop model looks like a latch ??
Post by jimi on Feb 1^st, 2005, 11:34pm

Hi, webmaster & others :

The D flip-flop model on this site looks like a simple latch, look forward an update if it really happens.
If not, please forgive a novice in Verilog-AMS modeling.

Jimi

Title: Re: The D flip-flop model looks like a latch ??
Post by Mighty Mouse on Feb 2^nd, 2005, 8:25pm

What is the difference between a latch and a D flip-flop?

-MM-

Title: Re: The D flip-flop model looks like a latch ??
Post by Mighty Mouse on Feb 2^nd, 2005, 8:42pm

I found a description of the difference at http://www.asic-world.com/digital/questions.html.

Quote:

What is the difference between a LATCH and a FLIP-FLOP?

Latch is a level sensitive device and flip-flop is edge sensitive device
Latch is sensitive to glitches on enable pin, where as flip-flop is immune to gltiches.
Latches take less gates (also less power) to implement then flip-flops
Latches are faster then flip-flops

They then go on to say that a flip-flop can be built from latches as follows

In this figure it seems the essential difference is a extra half clock cycle delay in the output.

But then in
http://dept-info.labri.u-bordeaux.fr/~strandh/Teaching/AMP/Common/Strandh-Tutorial/flip-flops.html they define the difference as follows ...

Quote:

Both latches and flip-flops are circuit elements whose output depends not only on the current inputs, but also on previous inputs and outputs. The difference between a latch and a flip-flop is that a latch does not have a clock signal, whereas a flip-flop always does.

This is the definition I am used to.

So it seems like the terms latch and flip-flop are not used consistently by engineers.

- MM -

Title: Re: The D flip-flop model looks like a latch ??
Post by Paul on Feb 3^rd, 2005, 6:40am

Hi Jimi and Mighty Mouse,

a latch can also be sensitive to a clock, but in that case it is sensitive to its level and not to its edge like a FF. It seems to me that the cross statement with dir=1 is sensitive to the rising clock edge. So the model is a FF, not a latch.

Paul

Title: Re: The D flip-flop model looks like a latch ??
Post by jimi on Feb 3^rd, 2005, 7:18pm

Hi, Paul :

A DFF output at clock edge N should be the data it latched in clock edge (N-1), the model just output the data at clock edge N.
A DFF should keep information of eariler state which is not found in the model.

Thanks you guys' response on this topic.
Jimi

Title: Re: The D flip-flop model looks like a latch ??
Post by Paul on Feb 4^th, 2005, 1:03am

Sorry Jimi,

I believe you mix up some things. When you are talking about latches, you cannot consider edges, you must consider levels. Suppose the FF is sensitive to the rising clock edge. While the clock is low, the first latch latches the input signal. When the clock goes high, the first latch will keep its state and the second latch will latch the output of the first one. This means that at the rising clock edge, the output takes the value of the input just before the rising edge occured.
Personally, I prefer to look at the FF simply like this:
The output gets the value of the input at the rising clock edge (neglecting set-up and hold times).

The model does hold the information: as long as there is no new rising clock edge, the output is not updated.

Paul