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Design Languages >> Verilog-AMS >> simulate verilog-a with nanosim
https://designers-guide.org/forum/YaBB.pl?num=1107501604

Message started by hygiea on Feb 3^rd, 2005, 11:20pm

Title: simulate verilog-a with nanosim
Post by hygiea on Feb 3^rd, 2005, 11:20pm

I had built a verilog-a beh model in Cadence. Then simulate the model in nanosim. It can work, but the result is wrong, what's the matter?

Title: Re: simulate verilog-a with nanosim
Post by Andrew Beckett on Feb 4^th, 2005, 11:49pm

I don't know nanosim (not surprising given I work for Cadence), but do you really expect anyone to be able to answer this?

Do you think we have ESP? How is anyone supposed to be able to figure out what the problem when all you've said is that it doesn't work?

Probably posting the model would be a good idea, and also explaining about exactly how it doesn't work.

Andrew.