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Message started by Richard on Dec 8^th, 2004, 11:31am

Title: DC/DC Buck's Phase Margin analysis using spectre ?
Post by Richard on Dec 8^th, 2004, 11:31am

Hi,
Has anyone use the spectre to analysis DC/DC buck converter phase margin ? We can use it in the switched-capacitor filter analysing the frequency response, so I think it can be used for loop-analysis in DC/DC converter.....if not possible, perhaps we can use the VERILOG-AMS in Cadence ?

Thanks.

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Eugene on Dec 8^th, 2004, 2:27pm

I've used SPICE for years to analyze the loop gain (gain and phase margin) of buck DC/DC converters and I am certain Spectre can do the same. However, I suspect you meant to ask about SpectreRF. To use Spectre, you would have to use a state space averaged model. The state space averaged model replaces the switch with an ideal DC/DC transformer. The more interesting approach, and probably the one you are asking about, is to apply SpectreRF directly to the time-varying model, perhaps even to the device level model. I think it would work for a pwm converter with a fixed switching frequency. I have always wanted to try it but never had the opportunity. I am not so sure about a resonant converter or any converter where the frequency can vary.

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Richard on Dec 8^th, 2004, 5:18pm

Thanks Eugene for the reply.
I wish to have simulations (determining phase margin) directly on the transistor level schematics. We have good results using PSS analysis of spectre on switched-capacitor filter and PLL systems, why not on a PWM DC/DC converter ?
Maybe you can say it being lazy.... ;), but I try to avoid using State-Space model, as the system can be complex and I might overlook some critical parasitics.
By the way, I am also interested and hope you can describe alittle more on how you use SPICE to analyse loop gain for buck ? do you construct a macro-model ? Do you use PSPICE or HSPICE ? How is the accuracy and any documentation to get me started ? such as an example ?

Thanks alot !! :)

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Frank Wiedmann on Dec 9^th, 2004, 12:26am

I have not tried this, but I think you should be able to use the method described in the article http://ieeexplore.ieee.org/xpl/abs_free.jsp?arNumber=900125 by simply replacing the AC sources with PAC sources. The article explains how Spectre's stb analysis is working.

Ken, how about implementing a pstb analysis in SpectreRF?

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Ken Kundert on Dec 9^th, 2004, 1:14am

Frank,
PSTB is a good idea. I'll pass on the request.

-Ken

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Eugene on Dec 9^th, 2004, 8:59am

Richard,
I hope this is readable. I had some trouble with the web page.

I agree with you that parasitics affect the analysis but I ususally do the state space averaged models anyway because: (1) the more complex the system, the more I learn about it by building a state space averaged model;(2) I rarely know the parasitics, especially those of external magnetics, accurately enough to justify skipping the state space averaged model.

I will post this message in pieces to circumvent some of the problems I'm having with this website.

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Eugene on Dec 9^th, 2004, 9:17am

In my previous life as a power electronics engineer, I implemented state space averaged models as macro models. If I were to build one today I would use VerilogA. If you do not have access to VerilogA, then you must resort to the old marcro models. For a buck converter, you replace the mosfet and catch diode with a nonlinear current-controlled-current source and a nonlinear voltage controlled voltage source. The voltage source sense the input filter capacitor voltage and a voltage numerically equal to the duty cycle. The voltage souce is nonlinear because the output voltage equals the product of the two sensed voltages. The voltage source drives the output inductor. The current source senses the output inductor current and the duty cycle signal and loads the input filter capacitor with the product of the two sensed signals. The current source may require a non-linear voltage controlled voltage source to perform the multiplication because if memory serves, there is no nonlinear current source that senses voltage and current in SPICE.

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Eugene on Dec 9^th, 2004, 9:26am

The above macro model is only good for the continuous conduction mode; it does not work if the inductor current periodically drops to zero amps. However, there are marcomodels that automatically switch between continuous and discontinuous state space averaged models on the fly. I will list a reference by Chen and Rodriquez later.

For a simple voltage model converter, the duty cycle is proportional to the error amplifier output. For a current mode converter, duty cycle is linear combination of output voltage and inductor current.

The nonlinear state space averaged macro models simulate large signal transient behavior and SPICE automatically linearizes them for small signal AC analysis (gain and phase margin). To break the loop for gain and phase margin analysis, insert a DC voltage source in series with the duty cycle. Set the DC voltage to zero and make the AC magnitude unity. Run an AC analysis. The magnitude of the loop gain equals the magnitude of the ratio of the voltage on duty cycle side of the DC source to the voltage on the other side. The phase margin equals the phase of the same ratio.

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Eugene on Dec 9^th, 2004, 9:46am

As for references, the first paper on state space averaging dates back to the early 70s and was written by Drs. Wester and Middlebrook. Dr. Cuk developed a more formal mathematical framework for state space averaging shortly after. I believe the first paper on state space averaging for current mode converters was by R.B. Ridley. I believe there are more recent books in print but here's some older ones from my library:

Severns and Bloom, "Modern DC-to-DC Switchmodel Power Converter Circuits". Van Nostrand Reinhold.
This book discusses various topologies and state space averaged models.

Steven Sandler, "SMPS Simulation with SPICE3". McGraw Hill.

Papers on macro modeling:

V. Bello. "Computer Aided Analysis of Switching Regulators Using SPICE2". IEEE PESC, 1980 Record.

J. Chen and R. Rodriguez, "Duo-Mode Nonlinear State Space Averaged SPICE Model of a Current Mode Buck Converter", APEC 1988.

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Eugene on Dec 9^th, 2004, 10:02am

I forgot to comment on the accuracy of state space averaged models. The state space averaged models start to break down between 1/10 and 1/2 the switching frequency. Also, as you said, parasitics can cause inaccuracies. For example, the state space averaged model can not simulate the effects of glitches in the sensed inductor current caused by the catch diode's reverse recorvery transient.

There are a few papers on sampled data effects that extend the accuracy of the state space model right up to half the switching frequency but since it is risky to push the loop gain's cross over frequency out that far, such papers are mainly of academic interest.

Most of the time, I found the state space averaged models predicted phase margins to within 5 to 20 degrees of measurements, depending on how well I knew the true parameter values.

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Richard on Dec 9^th, 2004, 10:26am

Thanks Eugene and Frank.
Frank : I am trying to use PAC for the sims, hopefully it will turn out okay. The question I have would be that we can see the gain response from PAC, can we also use it for phase response ?

Eugene : thanks for the advice. One of the problem with state-space would be that depending on the designer's skill set on doing the model, we might not get correct answers. Also, customer(some of them are really dumb, it takes alot time ot explain State-space to them) usually would question the equivalent model and hope we use some standardized or commerical well-established tools. By the way, do you prefer the MATLAB or SPICE method ? :)

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Eugene on Dec 9^th, 2004, 11:38am

For simulating power electronics I prefer SPICE. Matlab could do it but it is much easier to draw out the schematic for SPICE than to derive the circuit equations for matlab and re-invent the integration wheel.

As for state space averaging versus SpectreRF, I think it would be far easier to explain state space averaging than SpectreRF. I would think there are just as many ways, if not more, to get the SpectreRF simulation wrong as there are to get the state space averaged model wrong. In the power electronics arena, state space averaging is a proven method of analysis that has been thoroughly documented over the last 30 years. I am not aware of any documentation about applying SpectreRF to power electronics. Ideally, one would use both state space averaging and SpectreRF and make sure the two results agreed. In my opinion, new methods should never make old methods obsolete, they should instead provide an extra level of confidence. If I were the customer or technical reviewer, I would not trust an analysis from an engineer who simply plugged in the schematic, pressed the run button, then presented the results without some sort of check against classical methods.

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Frank Wiedmann on Dec 9^th, 2004, 11:37pm

Richard wrote on Dec 9^th, 2004, 10:26am:

Frank : I am trying to use PAC for the sims, hopefully it will turn out okay. The question I have would be that we can see the gain response from PAC, can we also use it for phase response ?

I would suppose so (but, like I said, I have not tried it).

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Ken Kundert on Dec 10^th, 2004, 12:05am

One thing to keep in mind is that PAC will give you the small-signal gain. Stability will depend on the large signal characteristics. The large-signal characteristics may be the same as, or at least very similar to, the small-signal characteristics, but I don't know. Like Frank, I have never tried these simulations.

-Ken

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Richard on Jan 4^th, 2005, 4:11pm

Hi,
I couldn't even do a gain-phase analysis on a linear feedback amplifier, let alone the switching DC/DC.
I find that having the loop-cutter i.e. breaking the loop and subitute with a RC to pass the DC and block the AC really screw up the PSS analysis.
I wonder if anyone has tried using the PSS for a simple case of feedback amplifer ?
Thanks. :)

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Ken Kundert on Jan 4^th, 2005, 5:25pm

One should never cut the feedback loop, whether you are using PSS or not. It leads to both simulation problems and lousy results. It is much better to either use the stability analysis in Spectre or the techniques outlined in my book (Designer's Guide to Spice & Spectre, section 3.4.1 on characterizing feedback amplifiers).

-Ken

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Frank Wiedmann on Jan 4^th, 2005, 11:43pm

You also might want to take another look at my reply #3 to this topic. That method does not cut the loop, so if your original circuit converges, the circuit with the PAC sources inserted should do so as well.

You can find an implementation of this method for AC analysis in LTspice (free, see http://www.linear.com/company/software.jsp) at http://groups.yahoo.com/group/LTspice/files/Examples/Educational/LoopGain_Probe/ (free registration required).

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Richard on Jan 6^th, 2005, 12:16am

Thanks Frank and Ken for your prompt reply.

Frank : I downloaded the LT files. Pardon my knowledge, I find that to determine the voltage loop gain and phase response, you just need a AC=1, DC=0 voltage source inserted in the loop. (e.g. at the output and input gate of unity feedback amplifier). Why do we need to determine the current gain and subsequently : (Gv*Gi-1)/(Gv+Gi+2) function ?

I am running the DC/DC with just the voltage source (pac=1) inserted with PSS and PAC analysis, hopefully I have some good results soon.

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Frank Wiedmann on Jan 6^th, 2005, 11:31pm

You need to determine both voltage and current gain in order to properly account for loading effects. See http://www.stanford.edu/class/ee214/handouts/h21_lecture15.pdf (and http://www.stanford.edu/class/ee214/handouts/h20_lecture14.pdf as background information) or the articles mentioned in the LTspice example.

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by richard88 on Jan 9^th, 2005, 2:05pm

Frank : Appreciate so much for the link & info. From the reading, I think if you need to take into account of comprehensive loading such as capacitive loading, the current gain measurement would be necessary. Anyway, it seems that the spectre still couldn't resolve to converge to a solution, error prompt : Zero diagonal found in Jacobian at `xextfet.8' and `xextfet.8'.

Eugene : Do you happen to know any good reading article on the design of oscillator ramp for the buck converter ? I couldn't find one, and I find it pretty important as it is part of the modulator loop gain. :-/

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Eugene on Jan 9^th, 2005, 5:03pm

I assume you have a pwm converter with either straight voltage mode control or current mode control. In either case, the frequency of the ramp limits your loop gain crossover frequency and the amplitude of the ramp scales the overall loop gain. Furthermore, any glitches in the ramp can cause all sorts of stability problems. Straight voltage mode control is fairly simple. The loop gain is proportional to the inverse of the amplitude of the ramp. Current mode control is more complex because you actually have two ramps: the same ramp you have for voltage control and in addition, a current compensation ramp to stabilize the current loop. I can recommand a few papers on current compensation but I am not sure they will be easy to find because they are somewhat old:

1. R.B Ridley, "A New Small-Signal Model for Current-Mode Control". Power Conversion and Intelligent Motion Conference proceedings, Oct. 16-19, 1989.

2. R.D. Middlebrook, "Topics in Multiple-Loop Regulators and Current-Mode Programming. IEEE Power Electronics Specialists Conference proceedings, June 26-29, 1989.

3. R.D. Middlebrook and S. Cuk. "Advances in Switched-mode Power Conversion". TESLAco.

You should find a wealth of papers on current mode control in the archives of the IEEE power electronics specialists conference. I suspect most papers will be at least 10 years old.

As I re-read your question, it occurs to me that perhaps you are asking about circuit design, not systems design. There are many ways to generate a ramp. Most power control chips generate it internally. If you are designing the ramp circuitry yourself, you could try texts such as
Millman and Taub, "Pulse, digital, and switching waveforms". McGraw Hill. This is an older text based on bipolar transistors. Something similar for newer technologies may exist. The main thing to worry about is keeping the ramp clean. As I said before, any imperfection in the ramp will adversely affect performance.

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by richard88 on Jan 9^th, 2005, 6:43pm

Eugene,
Thanks for your prompt and informative reply ! Wow :o, I'm learning alot from this forum. Yes, other than the first ref, I couldn't get hold of the other two.
No, I am still refering to the design of ramp for the voltage-mode @ system level. All I know is the modulator gain is 1/Vramp(p-p), like you mentioned. So it seems like smaller Vramp voltage, the higher the gain, but how small can it go before the noise overwhelms it, is 50mV reasonable? Also, other than stability, does Vramp impact other parameters such as line, load regulation ? Also, how should we pick the DC offset of the ramp ?
Please list any reference, no matter how old, I'll try to search for them.
Thanks. ::)

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Frank Wiedmann on Jan 9^th, 2005, 11:39pm

richard88 wrote on Jan 9^th, 2005, 2:05pm:

Anyway, it seems that the spectre still couldn't resolve to converge to a solution, error prompt : Zero diagonal found in Jacobian at `xextfet.8' and `xextfet.8'.

Does your circuit converge without the additional PAC source? If so, you might want to contact Cadence support because that would seem like a bug to me.

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by jws on Jan 10^th, 2005, 2:10am

Hi, do you try the circuit in
http://ieeexplore.ieee.org/xpl/abs_free.jsp?arNumber=900125
it has a simple circuit with RC feedback.

Have you try pac for the DC/DC buck?

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by richard88 on Jan 10^th, 2005, 10:30am

jws : Yes, I used PSS & PAC for analysis.

FInally, I have some results but I have to set the PSS option to traponly for the integration method instead of gear2only (usually this is recommended right ?)
Can anyone explain why traponly works in this case ?
Thanks. :)

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Eugene on Jan 10^th, 2005, 12:13pm

Richard88,
As you mentioned, the ramp should be large enough to overwhelm noise at that node. By "noise", I don't just mean stochastic signals. I include deterministic interference such as diode reverse recovery transients that may effectively sneak into the ramp signal. Yes, a larger ramp will reduce loop gain, but I would think you could easily make that up in the error amplifier, as long as the "noise" is not coming through the error amplifier. Neglecting noise for now, I believe the ramp only affects closed loop performance through the loop gain. So as I said, if you must use a large ramp I think you can make it up somewhere else in the loop. 50mV seems small to me but I've been away from power electronics for a few years. As for DC offset, I would align it with the output of the error amplifier to maximize the maximum dynamic range of the feedback loop if possible.

I don't remember any references specifically on voltage mode ramp design. Sorry. However, a state space averaged model should make quick simulation work of any study you need to perform to study the ramp :-)

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by jws on Jan 10^th, 2005, 6:53pm

Hi,Richard88
you can adjust several other parameters for pss.
Would you give me a copy of you netlist. I can try it for
you. If the pac loop gain you got is the same as the LTspice.

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by jws on Jan 13^th, 2005, 2:11am

Hi, Eugene
Have you compare the results of spice state space averaged model and the spectreRF
result for DC/DC buck. If there are some different? Do you think which is more accurate?

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Eugene on Jan 13^th, 2005, 9:06am

Jws,

I have always wanted to apply SpectreRF to power electronics but never had the chance to complete the job. I was more or less dragged kicking and screaming from power electronics into RF. I've done state space averaging and used SpectreRF (for RF circuits). I expect SpectreRF to be more accurate than state space averaging. I would not be surprised if SpectreRF could simulate the closed loop response to glitches in the voltage and/or current compensation ramps if one could model the sneak path accurately. However, I do not think SpectreRF makes state space averaging obsolete. Unlike SpectreRF, state space averaging can give you closed form expressions for all the transfer functions of interest. Such closed form expressions can give the designer insight that can save him/her hundreds of SpectreRF simulations. Also, if you want to simulate high level control functions you may want to add VerilogA models that have hidden state. Last I heard, SpectreRF can't handle hidden state. I would use state space average models during the early phases of the design then check the design with SpectreRF. I would also use SpectreRF for bottom up analysis. In short, SpectreRF should be more accurate than state space averaging but I absolutely do not consider it a replacement for state space averaging.

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by richard88 on Jan 14^th, 2005, 10:31am

Eugene,
I have got some results from spectre in running some simple examples of buck dc/dc, the results seems to be okay. It seems to be also modelling the delay through the digital driver driving the power switches which can be critical in performing closed loop response, as the extra pole from the delay might just cause the system to be unstable. I really wish there are more people try out and compare notes. I think if there is an article (or even book) from using spectre on DC/DC converter, it should be well-received. :)

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Ken Kundert on Jan 14^th, 2005, 1:06pm

Richard,
I think you are on the leading edge. Consider writing something for those that follow.

-Ken

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Eugene on Jan 14^th, 2005, 2:00pm

Richard88,

Thanks for the information. In the past, I've included such delays in my state space averaged models by inserting a properly terminated transmission line. But I am curious about your simulation. Did you mean to say SpectreRF instead of Spectre? If that is true and you are simulating digital circuitry, are you modeling the digital parts at the device or gate level or are you using VerilogA? If you are using VerilogA and SpectreRF, have you encountered a hidden state problem? How is your run time and how big is your circuit?

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by richard88 on Jan 15^th, 2005, 11:27am

For those circuits that I'm running now, it seems not much different in results between using just Gv or (Gv*Gi-1)/(Gv+Gi+2) function, anyone came across similiar stuff ?
Also, I have run on one circuit, using the method of just Gv (and also the whole Gv, Gi function), the result is major different at about 50MHz onwards compared to using the "Low-pass filter" loop-cutter method, not sure which one to trust (the results from the loop-cutter seems more decent).

Thanks. :)

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Frank Wiedmann on Jan 16^th, 2005, 11:41pm

You probably have put your probe in a place in your circuit where Gi is very large. As can easily be seen, the result of the formula is very close to Gv in this case.

Personally, I would not trust the result of any loop gain simulation method that breaks the loop. There are just too many places where you can make an error when setting it up.

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Eugene on Jan 17^th, 2005, 8:27am

What is the switching frequency of your converter? If it's on the order of a few MHz or less, from a loop gain standpoint I don't think you should care about what happens at 50MHz. Your loop should cross over way below that and remain low. If the switching frequency was way below 50MHz and there was something interesting at 50MHz, I would analyze 50MHz performance with open loop models, perhaps one for each switch position. Or, I might perform a closed loop simulation just to compute the steady state duty cycle, then drive the switch with that duty cycle in an open loop fashion to study 50MHz.

If you broke the loop with a voltage source at a point where the downstream impedance is much higher than the upstream impedance, I don't think you'd see much difference when you corrected for loading. I would expect the difference to show up only at very high frequencies, frequencies where the impedances start to approach and possible cross each other.

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by richard88 on Jan 21^st, 2005, 12:13pm

Thanks for the reply, Frank and Eugene.
I keep trying a few more sims, and actually realized that (perhaps) the gain, phase response starts to have "spectrum replica" at switching frequency (1MHz....the clock), so I guess that's why you have those.... just wonder if there is a way to get rid of those nasty "noise"... :)

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Eugene on Jan 21^st, 2005, 7:52pm

Hi richard88,

For switch mode power supplies, small signal pertubations about the steady state conditions can be modeled by a continuous time system with a sampler at the switch. (Look for an 80s paper by Billy Lau and Dr. Middlebrook. I think Marty Schlect's book may also have a chapter on sampled data models of power converters.) If you break the loop right after the sampler, indeed you will see a periodic transfer function and must resort to z-domain stability theory... keep the poles inside the unit circle. However, if you break the loop at a continuous time node, you should not see a periodic transfer function because the loop should have a low pass nature. If at the continuous time node you see a loop gain with magnitude anywhere near unity past 1/10 the switching frequency, you are almost certainly asking for stability problems.

Note that in most sampled data control systems, the sampler is followed by a DAC, which is mathematically a sample and hold. I this case, there is no sample and hold. There is only the power supply filter.

The replicated spectra you see could be real and if they are, you should probably reduce your cross over frequency, either by reducing gain, lowering the corner frequency of your filter, and/or changing your compensation.

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by richard88 on Jan 22^nd, 2005, 8:20pm

Thanks Eugene for the insightful analysis.

[ However, if you break the loop at a continuous time node, you should not see a periodic transfer function because the loop should have a low pass nature.

**I break at the resistor feedback (to the error amp). I think this should be okay. I still think there should be a periodic function, even at the output or the resistor feedback point, because you can see the voltage ripple of clock freq.

If at the continuous time node you see a loop gain with magnitude anywhere near unity past 1/10 the switching frequency, you are almost certainly asking for stability problems.

Note that in most sampled data control systems, the sampler is followed by a DAC, which is mathematically a sample and hold. I this case, there is no sample and hold. There is only the power supply filter.

The replicated spectra you see could be real and if they are, you should probably reduce your cross over frequency, either by reducing gain, lowering the corner frequency of your filter, and/or changing your compensation.[/quote]

**I get to know that the entire loop bandwidth has to be smaller than the clock freq, but didn't know it has to be 1/10......so if fclk=1MHz, the fbw<100kHz, is there any theory or intuitive reasoning behind this (especially like you mentioned the stability issue). :)

Also, could you recommend any classic papers on the "digital gate-delay induced poles " or modelling of delay.
Thanks.

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Eugene on Jan 23^rd, 2005, 9:00pm

Richard88,

1) If you break your loop at the error amplifier (which is an continuous time node), I agree that you may see a bump at the switching frequency but I do not think you will see a periodic transfer function. The filter should attenuate higher harmonics more than lower harmonics. In my opinion, you see ripple at that node not because there is an instability but because the system is time varying, it's driven by a fixed clock operating at the ripple frequency.

2) Crossing the loop below 1/10 the switching frequency...This is a rule of thumb. 1/20 would be even better if you can afford it. If you violate this rule, you had better be have ultra-accurate components and a sampled-data model that accurately models all delays...and you had better now those delays accurately. The point I'm trying to make is that component tolerances, temperature drifts, and un-modeled effects (like delays) usually punish those who violate the rule.

3) The references below may not directly help you but they may give you some ideas. Sorry they are so old. As I said before, my power electroncis experience is from a previous life; I've been out of the field for 8 years now so my library is somewhat out of date. There may be newer and better papers out by now.

1. Daniel Mitchell, "Pulsewidth Modulator Phase Shift", IEEE Transactions on Aerospace and Electronic Systems, AES 16 No. 3, pp 272-278, May 1980.

2. W. M. Polivka, P.R.K. Chetty, and R.D. Middlebrook, "State Space Averaged Modeling of Converters with Parasitic and Storage-Time Modulation", IEEE Power Electronics Specialists Conference, 1980 Record, pp119-143.

3. R.D. Middlebrook and Slobodan Cuk, "Advances in Switched-Mode Power Conversion. Chapter 15. Predicting Modulator Phase Lag in PWM Converter Feedback Loops. TeslaCo.

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by fantusox on Sep 8^th, 2006, 8:05pm

I am sorry but can anyone guide me on how you can break the loop for a current mode dcdc converter to see it's stability as I am dealing with a project on it? An example or any help will be grateful.

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by richard88 on Sep 13^th, 2006, 7:59am

fantusox wrote on Sep 8^th, 2006, 8:05pm:

I am sorry but can anyone guide me on how you can break the loop for a current mode dcdc converter to see it's stability as I am dealing with a project on it? An example or any help will be grateful.

current mode typically has two loops : main feedback and inductor current sense loop. To check the stability I would think that you should break the main feedback loop just like voltage mode.
I am not so sure about using pss to analyse the current mode as the inductor current sense waveform can be large signal and not sure if it can be analysed accurately. I would love to hear any comments.

Richard

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Eugene on Sep 13^th, 2006, 9:07am

I don't know of anyone who has fully demonstrated that PSS/PAC reliably computes the loop gain of a DC/DC converter. However, if you are using state space averaged models, you can compute the loop gain with AC analysis. If you want to break the current loop of a current mode converter, you will need to correct operating point, which means you will need a closed voltage loop too. If you insert your AC source (to break the loop) just before the DC/DC transformer, you break both loops. However, if you want to look at the current loop with the voltage loop opened in the AC sense, I don't know how to avoid using the larger inductor/capactor trick that everyone says is a bad ideal. I could be wrong, but I think Spectre's AC analysis is designed specifically for single loop systems.

In a multiloop system, it is often helpful to use a "sequential loop closure" procedure to assess stability. In the procedure, you examine the loops one at a time, usually from innermost to outermost. You start with all loops opened in the AC sense. After you assess a loop, you close it before assessing the next one. If you encounter an unstable inner loop, an outer loop can stabilize the system but to assess stability you must read the Nyquist criterion like a lawyer. A better way to assess stability would be to look at the closed loop poles. However, I have yet to see a very reliable pole/zero extraction tool for large circuits. Anyway, getting back to the sequential loop closure procedure, I'd be interested if someone knows of a better way to open the outer loops than to use large LC components.

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by richard88 on Sep 13^th, 2006, 11:35am

Eugene,
I think without using large cap/ind to block the ac signal, the method is to use the stb (based on middlebrook's double null injection theorem) analysis in spectre. Essentially, if you break the loop at the input of error amp (assume infinite input impedance), you can place a voltage source in between with DC=0, AC=1, run the ac sim and plot the vout/vin to get the gain and phase plot.

I have not read the Ridley's article which talk about small signal modelling of current mode converter. I would be interested to find out how the average model for modelling the two loops. I just find that with the inner loop which has inductor current waveform, to be compared at the comparator, seems to be a large signal behavior, which is not obvious for the model.

Richard

Eugene wrote on Sep 13^th, 2006, 9:07am:

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Eugene on Sep 13^th, 2006, 2:41pm

Hi Richard,

I have a rudimentary awareness of the stb probe (Middlebrook's method). My question is, does it work in general for a system that has multiple feedback loops?

I am certain you can use it on one loop while all other loops are closed. But to apply the Nyquist stability criterion, you must know how many RHP poles the other (closed) loops introduced. That requirement leads to the sequential loop closure method. The sequential loop closure method requires that you evaluate some loops with other loops opened. Does that mean we must break all loops with a stb probe? If so, how does Spectre know the sequence in which I want to assess the loops?

If each loop is assessed with all other loops closed, you will get the wrong answer. You can only use a sequential method by closing each loop only after it is assessed. If the stb probe really only works on one loop at a time, as I suspect, the sequential approach forces you to use large LC components to open the un-assessed loops without changing the DC operating point.

Many years ago, I used this method routinely on space craft power busses and motor control loops. Space craft power busses are powered by DC/DC converters and many of the loads are often DC/DC converters. Also, converters often use transformers to generate several output voltages, and those outputs are sometimes post regulated. Motor control loops often use current loops inside of position and/or velocity loops. All of these applications involve multiple feedback loops. The sequential loop closure approach has always given me answers consistent with transient simulations but I always had to use large LC components to apply the method. I'd love to avoid the LC components in a multiloop setting but I don't yet see how to do that.

-Eugene

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by richard88 on Sep 13^th, 2006, 6:21pm

Eugene,
As you said, the stb (I think) can only evaluate one loop.
Infact, I didn't know about the sequential loop evaluation method when analysing multiple loop.
I think this will be useful when dealing with linear regulator (LDO) when you have nested miller capacitor topology.
Can you point a reference or show us how to do the sequential loop evaluation ?
Thanks,
Richard

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Frank Wiedmann on Sep 13^th, 2006, 11:55pm

The stb analysis does not use Middlebrook's original method but an improved version of it, see http://www.thekunderts.net/ken/docs/c%26d2001-01.pdf. For a circuit with multiple loops, it can only be used if there is a critical wire that breaks all loops (see the article for details). The original reference for the sequential loop evaluation method is probably Bode's book "Network Analysis and Feedback Amplfier Design" (Reference 1 in the article).

For a better method to break multiple loops in Spectre, see Reply #14 of http://www.designers-guide.org/Forum/YaBB.pl?num=1155668476;start=all. However, you have to be aware that this is not quite the same as disabling the controlled sources of the active elements, which is what really would be required. Unfortunatly, transistor models usually do not give direct access to their internal controlled sources, so it is very difficult to apply this method in exactly the right way.

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Eugene on Sep 14^th, 2006, 12:01am

Richard,

I list three references below. I am certain the first is out of print. I pick such books up at garage sales and used book stores. I don't know if the others are in print. All three are fairly involved. I don't think such rigor is necessary if you have a solid understanding of the Nyquist stability criterion (NSC). The NSC states that a SISO system is stable if the Nyquist plot encircles the (-1,0) point CCW once for every RHP pole in the open loop system. ("open" refers the SISO loop in question). The trick to assessing a multiloop system as a sequence of single loop systems is to start with a known number of RHP poles. If we start with all loops open, the system is guaranteed to have zero RHP poles. As [3] suggests, it is sometimes most convenient to start with the highest bandwidth loop. For a current mode converter, that would be the innermost loop, the current loop. With all loops open, assess the loop gain of the first loop. It's ok if the first loop is unstable as long as you remember how many times the Nyquist plot encircled the (-1,0) point in the CW direction. That number equals the number of RHP poles the system has with just the first loop closed. The NSC does not depend how the plant was constructed or how any RHP poles came about; we can apply the NSC to the second loop with the first loop closed and all the rest open. The same argument applies to the next loop, and the next, and so on. Again, the key is to keep track of the number of RHP poles you add or subtract as you close each loop. By construction, when we close the last loop, we know how many RHP poles the system has with all loops closed.

There are other methods better suited for evaluating relative stability, depending on the system architecture. For example, for the case of one converter driving another, if the source impedance remains far below the load impedance over all frequencies, each loop can be assessed independent of the other. However, I have often gained valuable insight into system stability by checking my alternate methods against the sequential loop closure method.

[1] John Truxal, "Automatic Feedback Control System Synthesis". McGraw HIll. 1955. Pages 147-150.

[2] P. K. Sinha, "Multivariable Control, An Introduction". Marcel Dekker Inc. 1984. Pages 584-592.

[3] J. M. Maciejowski, "Multivariable Feedback Design". Addison-Wesley Publishing Co. 1989. Pages 137-142.

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by richard88 on Oct 3^rd, 2006, 10:34am

Eugene,
Typically, in current mode control, we have the current loop much faster than the voltage loop and we can assume that the current loop is a closed one right ? Unless you are concerned with the stability of the current loop. I supose the current loop stability should be a simple one, why would there by RHP zero ?

Thanks,
Richard

Eugene wrote on Sep 13^th, 2006, 2:41pm:

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Frank Wiedmann on Oct 4^th, 2006, 12:49am

Frank Wiedmann wrote on Sep 13^th, 2006, 11:55pm:

The stb analysis does not use Middlebrook's original method but an improved version of it, see http://www.thekunderts.net/ken/docs/c%26d2001-01.pdf.

This link does not work anymore. The article can now be found at http://www.kenkundert.com/docs/cd2001-01.pdf.

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Jason UCB on Oct 6^th, 2006, 4:43pm

I have a voltage-mode Buck PSS/PAC simulation that seems to work & gives correct small signal loop analysis ( a PSS/PAC loop analysis with double injection stability analysis). I have not tried multi-loop (current mode), or any modulator that requires hidden-state blocks.
I have this problem:
PAC works fine for normal behavioral blocks (analogLib). It also works fine for the ahdlLib comparator and real transistor level blocks.

When I place a verilogA (ahdlLib) logic block in the signal path, PAC fails. The PAC output is zero regarless of the input. There must be a solution for this? Its strange because PSS works fine with v-a logic, i'm just not sure if i'm missing something that would solve the PAC problem. Other than this i see no reason why you can't use PSS/PAC for switched mode power conversion.

Jason

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Ken Kundert on Oct 6^th, 2006, 11:43pm

By the definition of small signal, such signals will not affect the behavior of a circuit in a nonlinear fashion. As a result, they cannot pass through a thresholding input. It might be helpful to think about PSS/PAC as a two phase process, where the the circuit is linearized about the time varying operating point in the PSS phase and the small signal is applied in the PAC phase. As a result, the small signal cannot affect the time at which a cross function triggers. Also, if you have a comparator that switched from saturated low to saturated high between two time points, such that there is no time point in which the small signal would propagate from the input to the output, you would see no signal transmission in PAC.

-Ken

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Eugene on Oct 8^th, 2006, 10:20pm

Richard,

Sorry for the late reply. I was out of town.

You are right about current mode control: the current loop is much faster than the voltage loop, it is easy to stabalize, and you can usually focus on the outer loop with the current loop closed. I meant to bring up multiple loops in a more general context (multiloop motor controls, post regulated power supplies, peak power tracking solar arrays with output voltage regulation).

-Eugene

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Eugene on Oct 8^th, 2006, 10:29pm

Ken,

Jason claims that PSS/PAC works for his switch mode power supply when he uses behavioral comparators but not behavioral logic devices. What is the difference?

Jason,

I assume the two cases you mention are both brute force models, i.e. neither is a state space averaged model. Right?

-Eugene

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Ken Kundert on Oct 8^th, 2006, 10:39pm

To get PAC to work on a behavoiral comparator model you need a transition region where the gain is finite, and the PSS analysis must put some points down in that region.

-Ken

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Jason UCB on Oct 9^th, 2006, 9:03am

Ken, that makes complete sense & I assumed something like that was the case. I suppose it is necesary to write new behavioral logic models that have a 'linear' transition region. This is probably straightforward, but i don't cherish the thought of writing a new verilog-a logic library. I wonder if this will slow down the simulation? (probably not a big deal for this application...). I think with some new logic cells we will be up and running these simulations no problem.

eugene,
my simulation is not ss-average, it is just PSS/PAC on a mostly behavioral syncronous buck converter. to make convergence easier we made sure to clamp critical nodes with diodes & added enough parasitic cap to make the circuit 'realistic'. Other than that everything ran fine with a symmetric (naturally sampled) ramp modulator. I ran into problems trying to implement a dead time control circuit with behavioral logic (now i think this is a completely solvable problem).

Jason

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Jason UCB on Oct 17^th, 2006, 1:00pm

Some strange observations from PAC simulation:
I am now running a simple simulation with a ramp-comparator PWM followed by an inverter (see attached schematic).
Both the comparator and inverter have linear transition regions (based on tanh). The comparator gain is high (10000), the inverter gain is 100.

I get strange results from PAC: the input signal is 1V as expected. the output from the comparator (V1) is 1.43V (should be 1V?). rest of voltages as follows:
Vin=1
V1=1.4
V2=3.4
Vout~6

According to my understanding, this circuit should have unity gain of the PAC fundamental. This happens regardless of accuracy settings of PSS. especially strange that an RC network should have gain!

Any thoughts on this? I can try to clarify if necesary - this is critical to getting PWM (i.e. switch-mode power supplies) to work.

jason

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Eugene on Oct 17^th, 2006, 10:31pm

Which sideband are you using in your PAC analysis?

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Jason UCB on Oct 18^th, 2006, 10:37am

I don't have it in front of me, but I believe it is the '0' sideband. Whichever one corresponds to the fundamental of the PAC signal. I definitely checked to make sure I am not looking at some strange harmonic. my only guess is that this is related to the way PSS saves the steady state data - if there are discrete jumps in the PSS data could you end up with nonsensical gains from PAC? the problem with this thought is that it doesn't seem to be related to the min timestep - I tried setting this to 100pS & still get strange results.

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Eugene on Oct 18^th, 2006, 4:49pm

I wonder what would happen if you made the comparator transfer curve less steep (i.e. larger transition region).

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Jason UCB on Oct 18^th, 2006, 5:32pm

Yes, i've tried playing with the gains of both the comparator and the inverter cells. This does have an effect on the PAC results, but not in a rational way. I'm using a gain of ~100 right now.

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Ken Kundert on Oct 18^th, 2006, 7:25pm

You might want to try using a piecewise linear approximation rather than tanh(), and use cross functions at the corners so that you know the simulator spends some time within the linear region.

-Ken

Title: Re: DC/DC Buck's Phase Margin analysis using spect
Post by Jason UCB on Oct 20^th, 2006, 8:30pm

thanks for the advice.
I did try a piecewise linear model, with (virtually) identical results. I will try adding the cross functions & see what happens.

Title: Re: DC/DC Buck's Phase Margin analysis using spectre ?
Post by fet on Aug 6^th, 2009, 4:07am

Hope this article on EDN helps.

Periodic steady-state and small-signal analyses of switching regulators
http://www.edn.com/article/CA6579651.html

It compares the results between averaged model and PSTB simulation.

Title: Re: DC/DC Buck's Phase Margin analysis using spectre ?
Post by Frank Wiedmann on Aug 20^th, 2014, 2:24am

fet wrote on Aug 6^th, 2009, 4:07am:

Hope this article on EDN helps.

Periodic steady-state and small-signal analyses of switching regulators

It compares the results between averaged model and PSTB simulation.

This article is now at http://edn.com/design/analog/4327245/Periodic-steady-state-and-small-signal-analyses-of-switching-regulators.

Title: Re: DC/DC Buck's Phase Margin analysis using spectre ?
Post by AMSA on Sep 2^nd, 2014, 5:51am

Hi, I know that this thread is old but right now I am trying to do the same thing that Richard did and Jason too.

I am trying to get the frequency response of my dc-dc converter with the loop closed. I have inserted a VSIN with the PAC field at 1V and I have connected the positive terminal do the VSIN to the output of the converter and the negative to the input of the error amplifier.

After running the PSS + PAC analysis, I ask for the amplitude in dB20 on the left side of the VSIN and what I get is this:

http://postimg.org/image/b7d4v1mt3/

This result is strange because the response starts at 0dB and that shouldn't be right?

After that I tried to use the PSS + PSTB analysis replacing the VSIN source by the iprobe and the result that i got, asking for the loop gain option in the PSTB separator was this:

http://postimg.org/image/4lsqcxpr5/

If we go back to the PSS + PAC analysis, instead of selecting the left side of the VSIN source, selecting the right side I get almost the same shape and values of the PSS + PSTB analysis but inverted.

From what I have read all over the place I think that I am placing the PAC and/or iprobe in the correct place, I think I am configuring in the right way the analysis and I get this different results.

Can anyone help me out here? I am out of ideas and I don't have a clue on how to solve this.

Thanks in advance.

Kind regards.

EDIT: I forgot to tell that my converter is operating at very high frequency > 300MHz.

Title: Re: DC/DC Buck's Phase Margin analysis using spectre ?
Post by sheldon on Oct 29^th, 2016, 5:13am

AMSA,

Will say that if you want stability information, then you should use
periodic stability analysis not pac. PSTB is intended for this problem,
you can use PAC for audio susceptability and other measurements. It
is possible, see the attached picture for an example.

There was a paper a while ago on using pac before pstb became
available.
Frequency response analysis for switching converters in SPICE
without averaging, H. Deng, A. Q. Huang, Y. Ma, PESC 2004

The pstb example is from an AE-ware workshop of dc-to-dc converter
simulation with Spectre RF, contact your local Cadence AE for details.

Sheldon