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Modeling >> Behavioral Models >> model voltage controlled capacitor?
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Message started by nus_lin on Feb 14^th, 2005, 6:49am

Title: model voltage controlled capacitor?
Post by nus_lin on Feb 14^th, 2005, 6:49am

hi. I have a quesion to ask, and highly appreciate if anyone drop your comments.
i am working on a capacitive sensor, and i need to model it as a time-varying capacitor. i am thinking of model it as a voltage controlled capacitor. this behavior level model will be combined with circuit simulator- cadence to simulate the systematic behavior of my interface circuit. can someone tell me how to create such a model in cadence?
???

Title: Re: model voltage controlled capacitor?
Post by Eugene on Feb 14^th, 2005, 6:38pm

Do you have access to VerilogA?

Title: Re: model voltage controlled capacitor?
Post by nus_lin on Feb 14^th, 2005, 9:11pm

not sure, need to check it out. what should i do if i have access to verilogA?

Title: Re: model voltage controlled capacitor?
Post by Ken Kundert on Feb 14^th, 2005, 10:08pm

You can build a charge-based model as described in http://www.designers-guide.com/Modeling/varactors.pdf. In fact, with Verilog-A you can build the time-varying capacitor model directly. If you have Spectre you have Verilog-A.

-Ken

Title: Re: model voltage controlled capacitor?
Post by nus_lin on Feb 15^th, 2005, 6:30am

thank you, ken.

but as a circuit designing guy, i never create such a fully-customed component before. i just don't know how to access verilogA with cadence, can you recommend some quick online manual or briefly tell me how to do that?

thanks.

HE Lin

Title: Re: model voltage controlled capacitor?
Post by Andrew Beckett on Feb 17^th, 2005, 2:10pm

Well, the Verilog-A manual would be a good start!

Try actually looking at the documentation - either start by hitting "help" in one of the windows, or by typing "cdsdoc" at the UNIX prompt (or openbook if you're using an old version (prior to IC446)).

It's searchable - so you should be able to find suitable references relatively easily.

Regards,

Andrew.

Title: Re: model voltage controlled capacitor?
Post by nus_lin on Mar 18^th, 2005, 7:56am

thank you. Ken and Andrew, I have already finished the modeling of time-varying capacitor.
here i have something to share with other guys who may have similar problems.

Please follow the below steps to create a symbol out of the verilog-a code. Then you can instantiate this symbol in you design and make use of the same.

1) In CIW, File->New->Cell View

2) Give a Library name, Cell name and choose Tool as “VerilogA-Editor” from cyclic field and press OK.

3) This will open a VI editor. This will contain some default lines, delete these lines and paste your verilog-a code in this file.

4) Save the file by typing :wq in vi editor

5) This will create a veriloga view for this code.

6) After few seconds, it will ask if you want to create a symbol view for the same. Press Yes. This will create a symbol view for your code.

7) You may instantiate this symbol in your schematic and make use of the same.

Hope this helps.

Title: Re: model voltage controlled capacitor?
Post by jbdavid on Oct 12^th, 2005, 1:01am

For a treat.. before you start those steps..
visit www.nedit.org and download the executable for your OS & platform..
Also down load the contributed patternfiles for Verilog-A and Verilog-AMS..
after adjusting your path so the nedit executable is available on your path.. import the two pattern files (instructions in the file)
and save defaults after importing each..
--
now in the CIW command line type
>editor = "nedit"
and proceed thru the steps above..
I think you'll be happier with this editor than with vi..
(but I did Verilog-A modelling for 2 years before I found out about nedit in 1999.. )

Jonathan