The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> VHDL-AMS >> CLock Delays
https://designers-guide.org/forum/YaBB.pl?num=1108640950

Message started by jr81 on Feb 17^th, 2005, 3:49am

Title: CLock Delays
Post by jr81 on Feb 17^th, 2005, 3:49am

Hi I have created some code to use as a clock divider. I am creating 4 new clock signals. 2 of the clock signals are of the same frequency however one must be a delayed version of the other. I need to implement this for a Xilinx CPLD. Any suggestions on how to delay one of the clock signals.

Thanks in advance.