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Design Languages >> Verilog-AMS >> Verilog-AMS training
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Message started by learnams on Feb 23^rd, 2005, 5:35pm

Title: Verilog-AMS training
Post by learnams on Feb 23^rd, 2005, 5:35pm

Hi,

Are there any short training sessions for analog behavioral modeling in Verilog-AMS or VHDL-AMS? I am looking for some thing where instead of learning just by reading a book, we can have somebody explaining the concepts to us and try out some labs.

Thanks!

Title: Re: Verilog-AMS training
Post by Andrew Beckett on Feb 23^rd, 2005, 9:31pm

Cadence offer a "Virtuoso AMS Designer" class. See the course catalog at http://learning.cadence.com/ns-bin/docentnsapi/lms,learning.cadence.com,2151/?CMD=LOGIN&file=frameset.jsm

Expand the Custom IC Design part of the catalog, and you'll find it there.

This class explains not only how to use the tool, but the concepts in the Verilog-AMS language. There is a section on VHDL-AMS too.

More details at http://learning.cadence.com/ns-bin/docentnsapi/lms,learning.cadence.com,2151/SID%3DLEARNING.CADENCE.COM%3A61866-0000-0-3607762E-00BD5CA8,SVR%3Dlearning.cadence.com%3A61866,SQN%3D-92676654/?CMD=GET&FILE=catalog/activity.jsm&path=0%3AMain%20Catalog&ID=3428

Note, I'm not sure the duration is correct there. It was a 3 day class when I taught it recently. It's quite a good class, in my opinion.

Regards,

Andrew.