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Design Languages >> VHDL-AMS >> Delay with buffers in VHDL
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Message started by ratep2001 on Feb 25^th, 2005, 6:06am

Title: Delay with buffers in VHDL
Post by ratep2001 on Feb 25^th, 2005, 6:06am

I have the following problem: I want to implement large delays (50-100ns) on some signals in my VHDL code and fit them into a CPLD, and for that purpose I use chained buffers. However, I found out that although I use the attributes for preservation of nodes/signals ("syn_keep" for Synplify and "opt" for the optimizer), I cannot preserve more than one single buffer.

For example, in the code below I want to fit 7 buffers between the input and the output signal. However, I don't get 7 chained buffers in my pre-fit equations, but just a single buffer buf7 on my input signal. So I end up with just a few nanoseconds of delay, which is far from sufficient.

Is there any elegant way to create more than one buffer, and preserve it from collapsing? I can use either Synplify - Synplicity or Leonardo Spectrum - Menthor Graphics.

Best regards,
Petar

--------------------------------------
Example VHDL code

library ieee;
use ieee.std_logic_1164.all;

entity delay_block is
port
(
in_signal: IN STD_LOGIC;
out_signal: OUT STD_LOGIC
);

end;

architecture delay_block_arch of delay_block is

signal buf1, buf2, buf3, buf4, buf5, buf6, buf7: STD_LOGIC;

attribute syn_keep: integer;
attribute syn_keep of buf1, buf2, buf3, buf4, buf5, buf6, buf7: signal is 1;

attribute OPT: string;
attribute OPT of buf1, buf2, buf3, buf4, buf5, buf6, buf7: signal is "KEEP";

begin
buf1 <= in_signal;
buf2 <= buf1;
buf3 <= buf2;
buf4 <= buf3;
buf5 <= buf4;
buf6 <= buf5;
buf7 <= buf6;
out_signal <= buf7;

end delay_block_arch;